QSPI_csr Address Map
Module Instance | Base Address | End Address |
---|---|---|
i_qspi__qspi_csr__108d2000__qspiregs__SEG_hps2sdm_be_0x2000_0x1000
|
0x108D2000
|
0x108D20FF
|
Register | Offset | Width | Access | Reset Value | Description |
---|---|---|---|---|---|
cfg
|
0x0
|
32
|
RW
|
0x80780000
|
QSPI Configuration Register |
devrd
|
0x4
|
32
|
RW
|
0x00000003
|
Device Read Instruction Configuration Register |
devwr
|
0x8
|
32
|
RW
|
0x00000002
|
Device Write Instruction Configuration Register |
delay
|
0xC
|
32
|
RW
|
0x00000000
|
QSPI Device Delay Register |
rddatacap
|
0x10
|
32
|
RW
|
0x00000001
|
Read Data Capture Register |
devsz
|
0x14
|
32
|
RW
|
0x00101002
|
Device Size Configuration Register |
srampart
|
0x18
|
32
|
RW
|
0x00000200
|
SRAM Partition Configuration Register |
indaddrtrig
|
0x1C
|
32
|
RW
|
0x00000000
|
Indirect AHB Address Trigger Register |
dmaper
|
0x20
|
32
|
RW
|
0x00000000
|
DMA Peripheral Configuration Register |
remapaddr
|
0x24
|
32
|
RW
|
0x00000000
|
Remap Address Register |
modebit
|
0x28
|
32
|
RW
|
0x00000000
|
Mode Bit Configuration Register |
sramfill
|
0x2C
|
32
|
RO
|
0x00000000
|
SRAM Fill Register |
txthresh
|
0x30
|
32
|
RW
|
0x00000001
|
TX Threshold Register |
rxthresh
|
0x34
|
32
|
RW
|
0x00000001
|
RX Threshold Register |
irqstat
|
0x40
|
32
|
RW
|
0x00000000
|
Interrupt Status Register |
irqmask
|
0x44
|
32
|
RW
|
0x00000000
|
Interrupt Mask |
lowwrprot
|
0x50
|
32
|
RW
|
0x00000000
|
Lower Write Protection Register |
uppwrprot
|
0x54
|
32
|
RW
|
0x00000000
|
Upper Write Protection Register |
wrprot
|
0x58
|
32
|
RW
|
0x00000000
|
Write Protection Control Register |
indrd
|
0x60
|
32
|
RW
|
0x00000000
|
Indirect Read Transfer Control Register |
indrdwater
|
0x64
|
32
|
RW
|
0x00000000
|
Indirect Read Transfer Watermark Register |
indrdstaddr
|
0x68
|
32
|
RW
|
0x00000000
|
Indirect Read Transfer Start Address Register |
indrdcnt
|
0x6C
|
32
|
RW
|
0x00000000
|
Indirect Read Transfer Number Bytes Register |
indwr
|
0x70
|
32
|
RW
|
0x00000000
|
Indirect Write Transfer Control Register |
indwrwater
|
0x74
|
32
|
RW
|
0xFFFFFFFF
|
Indirect Write Transfer Watermark Register |
indwrstaddr
|
0x78
|
32
|
RW
|
0x00000000
|
Indirect Write Transfer Start Address Register |
indwrcnt
|
0x7C
|
32
|
RW
|
0x00000000
|
Indirect Write Transfer Number Bytes Register |
flashcmd
|
0x90
|
32
|
RW
|
0x00000000
|
Flash Command Control Register |
flashcmdaddr
|
0x94
|
32
|
RW
|
0x00000000
|
Flash Command Address Registers |
flashcmdrddatalo
|
0xA0
|
32
|
RO
|
0x00000000
|
Flash Command Read Data Register (Lower) |
flashcmdrddataup
|
0xA4
|
32
|
RO
|
0x00000000
|
Flash Command Read Data Register (Upper) |
flashcmdwrdatalo
|
0xA8
|
32
|
RW
|
0x00000000
|
Flash Command Write Data Register (Lower) |
flashcmdwrdataup
|
0xAC
|
32
|
RW
|
0x00000000
|
Flash Command Write Data Register (Upper) |
moduleid
|
0xFC
|
32
|
RO
|
0x00001001
|
Module ID Register |