indwr
Module Instance | Base Address | Register Address |
---|---|---|
i_qspi__qspi_csr__108d2000__qspiregs__SEG_hps2sdm_be_0x2000_0x1000
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0x108D2000
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0x108D2070
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Size: 32
Offset: 0x70
Access: RW
Bit Fields | |||||||||||||||
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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indwr Fields
Bit | Name | Description | Access | Reset | ||||||
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31:8 |
indir_wr_xfer_resv2_fld
|
RO
|
0x0
|
|||||||
7:6 |
indcnt
|
This field contains the number of indirect operations which have been completed. This is used in conjunction with the indirect completion status field (bit 5). It is incremented by hardware when an indirect operation has completed. Write a 1 to bit 5 of this register to decrement it. |
RO
|
0x0
|
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5 |
inddone
|
This field is set to 1 when an indirect operation has completed. Write a 1 to this field to clear it.
|
RW
|
0x0
|
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4 |
rdqueued
|
Two indirect write operations have been queued
|
RO
|
0x0
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3 |
indir_wr_rsvd_fld
|
RO
|
0x0
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2 |
rdstat
|
Indirect write operation in progress (status)
|
RO
|
0x0
|
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1 |
cancel
|
Writing a 1 to this bit will cancel all ongoing indirect write operations.
|
WO
|
0x0
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0 |
start
|
Writing a 1 to this bit will trigger an indirect write operation. The assumption is that the indirect start address and the indirect number of bytes register is setup before triggering the indirect write operation.
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WO
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0x0
|