indrd
Module Instance Base Address Register Address
i_qspi__qspi_csr__108d2000__qspiregs__SEG_hps2sdm_be_0x2000_0x1000 0x108D2000 0x108D2060

Size: 32

Offset: 0x60

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

indir_rd_xfer_resv_fld

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

indir_rd_xfer_resv_fld

RO 0x0

num_ind_ops_done

RO 0x0

ind_ops_done_status

RW 0x0

rd_queued

RO 0x0

sram_full

RW 0x0

rd_status

RO 0x0

cancel

WO 0x0

start

WO 0x0

indrd Fields

Bit Name Description Access Reset
31:8 indir_rd_xfer_resv_fld 

                     		
                     
                        RO
                     
                     
                        0x0
                     
                  

                  

                     7:6
                     
                        num_ind_ops_done
                     
                     
                        
This field contains the number of indirect operations which have been completed. This is used in conjunction with the indirect completion status field (bit 5). It is incremented by hardware when an indirect operation has completed.  Write a 1 to bit 5 of this register to decrement it. 

                     		
                     
                        RO
                     
                     
                        0x0
                     
                  

                  

                     5
                     
                        ind_ops_done_status
                     
                     
                        
This field is set to 1 when an indirect operation has completed. Write a 1 to this field to clear it.

                        

                           

                                 Value
                                 Description
                              

                                 0
                                 Indirect Op Not Complete 
                              

                                 1
                                 Indirect Op Complete operation
                              

                        

                     		
                     
                        RW
                     
                     
                        0x0
                     
                  

                  

                     4
                     
                        rd_queued
                     
                     
                        
Two indirect read operations have been queued

                        

                           

                                 Value
                                 Description
                              

                                 0
                                 No Queued Read 
                              

                                 1
                                 Queued Indirect Read
                              

                        

                     		
                     
                        RO
                     
                     
                        0x0
                     
                  

                  

                     3
                     
                        sram_full
                     
                     
                        
 SRAM full and unable to immediately complete an indirect operation. Write a 1 to this field to clear it."; indirect operation (status) 

                        

                           

                                 Value
                                 Description
                              

                                 0
                                 SRram Not Full 
                              

                                 1
                                 Sram Full- Cant complete operation
                              

                        

                     		
                     
                        RW
                     
                     
                        0x0
                     
                  

                  

                     2
                     
                        rd_status
                     
                     
                        
Indirect read operation in progress (status)

                        

                           

                                 Value
                                 Description
                              

                                 0
                                 No read operation in progress 
                              

                                 1
                                 Read Operation in progress
                              

                        

                     		
                     
                        RO
                     
                     
                        0x0
                     
                  

                  

                     1
                     
                        cancel
                     
                     
                        
 Writing a 1 to this bit will cancel all ongoing indirect read operations. 

                        

                           

                                 Value
                                 Description
                              

                                 0
                                 Do Not Cancel Indirect Read 
                              

                                 1
                                 Cancel Indirect Read
                              

                        

                     		
                     
                        WO
                     
                     
                        0x0
                     
                  

                  

                     0
                     
                        start
                     
                     
                        
 Writing a 1 to this bit will trigger an indirect read operation. The assumption is that the indirect start address and the indirect number of bytes register is setup before triggering the indirect read operation. 

                        

                           

                                 Value
                                 Description
                              

                                 0
                                 No Indirect Read 
                              

                                 1
                                 Trigger Indirect Read
                              

                        

                     		
                     
                        WO
                     
                     
                        0x0