devrd


Module Instance	Base Address	Register Address
`i_qspi__qspi_csr__108d2000__qspiregs__SEG_hps2sdm_be_0x2000_0x1000`	`0x108D2000`	`0x108D2004`

Size: 32

Offset: 0x4

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`rd_instr_resv5_fld` `RO 0x0`			`dummyrdclks` `RW 0x0`					`rd_instr_resv4_fld` `RO 0x0`			`enmodebits` `RW 0x0`	`rd_instr_resv3_fld` `RO 0x0`		`datawidth` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`rd_instr_resv2_fld` `RO 0x0`		`addrwidth` `RW 0x0`		`rd_instr_resv1_fld` `RO 0x0`		`instwidth` `RW 0x0`		`rdopcode` `RW 0x3`

devrd Fields

Bit Name Description Access Reset

31:29

rd_instr_resv5_fld

RO

0x0

28:24

dummyrdclks

 Number of dummy clock cycles required by device for read instruction.

RW

0x0

23:21

rd_instr_resv4_fld

RO

0x0

enmodebits

 Set this field to 1 to ensure that the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes.

Value	Description
0	No Order
1	Mode Bits follow address bytes

RW

0x0

19:18

rd_instr_resv3_fld

RO

0x0

17:16

datawidth

 0 : SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only 1 : Used for Dual Input/Output instructions. For data transfers, DQ0 and DQ1 are used as both inputs and outputs. 2 : Used for Quad Input/Output instructions. For data transfers, DQ0,DQ1,DQ2 and DQ3 are used as both inputs and outputs.

Value	Description
0	Read data transferred on DQ0. Supported by all SPI flash devices
1	Read data transferred on DQ0 and DQ1. Supported by some SPI flash devices that support the Extended SPI Protocol and by all SPI flash devices that support the Dual SP (DIO-SPI) Protocol.
2	Read data transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash devices that support the Extended SPI Protocol and by all SPI flash devices that support the Quad SP (QIO-SPI) Protocol.

RW

0x0

15:14

rd_instr_resv2_fld

RO

0x0

13:12

addrwidth

 0 : Addresses can be shifted to the device on DQ0 only 1 : Addresses can be shifted to the device on DQ0 and DQ1 only 2 : Addresses can be shifted to the device on DQ0, DQ1, DQ2 and DQ3

Value	Description
0	Read address transferred on DQ0. Supported by all SPI flash devices
1	Read address transferred on DQ0 and DQ1. Supported by some SPI flash devices that support the Extended SPI Protocol and by all SPI flash devices that support the Dual SP (DIO-SPI) Protocol.
2	Read address transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash devices that support the Extended SPI Protocol and by all SPI flash devices that support the Quad SP (QIO-SPI) Protocol.

RW

0x0

11:10

rd_instr_resv1_fld

RO

0x0

9:8

instwidth

 0 : Use Standard SPI mode (instruction always shifted into the device on DQ0 only) 1 : Use DIO-SPI mode (Instructions, Address and Data always sent on DQ0 and DQ1) 2 : Use QIO-SPI mode (Instructions, Address and Data always sent on DQ0, DQ1, DQ2 and DDQ3)

Value	Description
0	Instruction transferred on DQ0. Supported by all SPI flash devices.
1	Instruction transferred on DQ0 and DQ1. Supported by all SPI flash devices that support the Dual SP (DIO-SPI) Protocol.
2	Instruction transferred on DQ0, DQ1, DQ2, and DQ3. Supported by all SPI flash devices that support the Quad SP (QIO-SPI) Protocol.

RW

0x0

7:0

rdopcode

 Read Opcode to use when not in XIP mode

Value	Description
3	Read Opcode in Non-XIP mode
11	Fast Read in Non-XIP mode

RW

0x3