GPIO0 Address Map

DW_apb_gpio address block


Module Instance	Base Address	End Address
`i_gpio_0__gpio_csr__10c03200__DW_apb_gpio_addr_block__SEG_L4_SP_gpio0_0x0_0x100`	`0x10C03200`	`0x10C0327F`


Register	Offset	Width	Access	Reset Value	Description
`GPIO_SWPORTA_DR`	`0x0`	`32`	`RW`	`0x00000000`	Port A data register
`GPIO_SWPORTA_DDR`	`0x4`	`32`	`RW`	`0x0`	Port A Data Direction Register
`GPIO_INTEN`	`0x30`	`32`	`RW`	`0x00000000`	Interrupt enable register
`GPIO_INTMASK`	`0x34`	`32`	`RW`	`0x00000000`	Interrupt mask register
`GPIO_INTTYPE_LEVEL`	`0x38`	`32`	`RW`	`0x00000000`	Interrupt level
`GPIO_INT_POLARITY`	`0x3C`	`32`	`RW`	`0x00000000`	Interrupt polarity
`GPIO_INTSTATUS`	`0x40`	`32`	`RO`	`0x00000000`	Interrupt status
`GPIO_RAW_INTSTATUS`	`0x44`	`32`	`RO`	`0x00000000`	Raw interrupt status
`GPIO_DEBOUNCE`	`0x48`	`32`	`RW`	`0x00000000`	Debounce enable
`GPIO_PORTA_EOI`	`0x4C`	`32`	`WO`	`0x00000000`	Port A clear interrupt register
`GPIO_EXT_PORTA`	`0x50`	`32`	`RO`	`0x00000000`	Port A external port register
`GPIO_LS_SYNC`	`0x60`	`32`	`RW`	`0x00000000`	Synchronization level
`GPIO_ID_CODE`	`0x64`	`32`	`RO`	`0x00000000`	GPIO ID code
`GPIO_VER_ID_CODE`	`0x6C`	`32`	`RO`	`0x3231302A`	GPIO Component Version
`GPIO_CONFIG_REG2`	`0x70`	`32`	`RO`	`0x00039CF7`	GPIO Configuration Register 2
`GPIO_CONFIG_REG1`	`0x74`	`32`	`RO`	`0x001FF0F2`	GPIO Configuration Register 1