GPIO_LS_SYNC

         Name: Synchronization level
Size: 1 bit
Address Offset: 0x60
Read/Write Access: Read/Write


Module Instance	Base Address	Register Address
`i_gpio_0__gpio_csr__10c03200__DW_apb_gpio_addr_block__SEG_L4_SP_gpio0_0x0_0x100`	`0x10C03200`	`0x10C03260`

Size: 32

Offset: 0x60

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_1` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_1` `RO 0x0`															`GPIO_LS_SYNC` `RW 0x0`

GPIO_LS_SYNC Fields

Bit Name Description Access Reset

31:1

Reserved_1

Reserved bitfield added by Magillem

RO

0x0

GPIO_LS_SYNC

Writing a 1 to this register results in all level-sensitive interrupts being
synchronized to pclk_intr.
0  No synchronization to pclk_intr (default)
1  Synchronize to pclk_intr

Value	Description
0x0	No synchronization to pclk_intr
0x1	Synchronize to pclk_intr

RW

0x0