GPIO_INTEN
Name: Interrupt enable register
Size: 1-32 bits
Address Offset: 0x30
Read/Write Access: Read/Write
| Module Instance | Base Address | Register Address |
|---|---|---|
i_gpio_0__gpio_csr__10c03200__DW_apb_gpio_addr_block__SEG_L4_SP_gpio0_0x0_0x100
|
0x10C03200
|
0x10C03230
|
Size: 32
Offset: 0x30
Access: RW
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|
|
|
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
|
|||||||||||||||
GPIO_INTEN Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31:24 |
Reserved_1
|
Reserved bitfield added by Magillem |
RO
|
0x0
|
||||||
| 23:0 |
GPIO_INTEN
|
Allows each bit of Port A to be configured for interrupts. By default the generation of interrupts is disabled. Whenever a 1 is written to a bit of this register, it configures the corresponding bit on Port A to become an interrupt; otherwise, Port A operates as a normal GPIO signal. Interrupts are disabled on the corresponding bits of Port A if the corresponding data direction register is set to Output or if Port A mode is set to Hardware. 0 Configure Port A bit as normal GPIO signal (default) 1 Configure Port A bit as interrupt
|
RW
|
0x0
|