GPIO_CONFIG_REG2

         Name: GPIO Configuration Register 2
Size: 32 bits
Address Offset: 0x70
Read/Write Access: Read


Module Instance	Base Address	Register Address
`i_gpio_0__gpio_csr__10c03200__DW_apb_gpio_addr_block__SEG_L4_SP_gpio0_0x0_0x100`	`0x10C03200`	`0x10C03270`

Size: 32

Offset: 0x70

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_4` `RO 0x0`												`ENCODED_ID_PWIDTH_D` `RO 0x7`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`ENCODED_ID_PWIDTH_D` `RO 0x7`	`ENCODED_ID_PWIDTH_C` `RO 0x7`					`ENCODED_ID_PWIDTH_B` `RO 0x7`					`ENCODED_ID_PWIDTH_A` `RO 0x17`

GPIO_CONFIG_REG2 Fields


Bit	Name	Description	Access	Reset
31:20	`Reserved_4`	Reserved bitfield added by Magillem	`RO`	`0x0`
19:15	`ENCODED_ID_PWIDTH_D`	The value of this register is derived from the GPIO_PWIDTH_D configuration parameter. 0x0 = 8 bits 0x1 = 16 bits 0x2 = 32 bits 0x3 = Reserved	`RO`	`0x7`
14:10	`ENCODED_ID_PWIDTH_C`	The value of this register is derived from the GPIO_PWIDTH_C configuration parameter. 0x0 = 8 bits 0x1 = 16 bits 0x2 = 32 bits 0x3 = Reserved	`RO`	`0x7`
9:5	`ENCODED_ID_PWIDTH_B`	The value of this register is derived from the GPIO_PWIDTH_B configuration parameter. 0x0 = 8 bits 0x1 = 16 bits 0x2 = 32 bits 0x3 = Reserved	`RO`	`0x7`
4:0	`ENCODED_ID_PWIDTH_A`	The value of this register is derived from the GPIO_PWIDTH_A configuration parameter. 0x0 = 8 bits 0x1 = 16 bits 0x2 = 32 bits 0x3 = Reserved	`RO`	`0x17`