This datasheet lists the performance and logic element (LE) usage for
a typical implementation of a
Nios® II soft processor and peripherals.
Nios® II processors are configurable and
designed for implementation in
FPGAs. The following
Nios® II processors cores
were used for these benchmarks:1
Nios® II/f “fast” processor is designed for high
performance and has the most configuration options, some of which are
unavailable in the
Nios® II/e processor.
Nios® II/e “economy” processor is designed for the
smallest possible logic size while still providing adequate performance.
The default options for the
Nios® II processor were chosen for these benchmarks, unless specified otherwise.
Note: Results may vary slightly
depending on the version of the
software, the version of the
Nios® II processor,
compiler version, target device and the configuration of the processor. Also, any
changes to the system logic design might change the performance and LE usage. All
results are generated from designs built using the Platform Designer tool.
The Dhrystone MIPS (DMIPS) reports were obtained using the Dhrystone
2.1 benchmark. You can download the Dhrystone 2.1 benchmark software with the Fast
Nios® II Hardware
Design Example on the Intel FPGA
website. For more information about the Dhrystone 2.1 benchmark software and the
Fast design example, refer to the readme.txt file which is
included in the design example page.
The CoreMark software can be registered and downloaded at www.eembc.org.
Nios® II Classic and
Nios® II benchmark data are very similar. The
Nios® II processor was used to create the systems which gave the data
values reported in this document. Please refer to the older versions of this
document for values associated with the Classic cores.
The resource utilization results were generated using moderate
Analysis, Synthesis and Fitter settings in the Quartus Prime software. These results
represent typical results.
Table 1. System Configuration for Nios II Performance
Nios® II/s core is only available with the
Nios® II Classic soft processor.
2 This benchmark is compiled with the gcc -o3
switch for optimised performance.
3 The RAM controller for
device is based on DDR3 SDRAM Controller with
Arria® 10, and
Stratix® 10 devices, the RAM controller is based on the respective device
4 Results were generated using the analysis, synthesis
and fitter settings in
5 The RAM controller for the
device is based on DDR3 SDRAM Controller with UniPHY. For
Arria® 10, and
Stratix® 10 devices, the RAM controller
is based on the respective device IP.
Document Revision History
Table 5. Document Revision History
Cyclone® 10 GX, and