Nios® II Performance Benchmarks

ID 683629
Date 5/14/2020
Public

1. Overview

This datasheet lists the performance and logic element (LE) usage for a typical implementation of a Nios® II soft processor and peripherals. Nios® II processors are configurable and designed for implementation in Intel® FPGAs. The following Nios® II processors cores were used for these benchmarks:1

  • Nios® II/f—The Nios® II/f “fast” processor is designed for high performance and has the most configuration options, some of which are unavailable in the Nios® II/e processor.
  • Nios® II/e—The Nios® II/e “economy” processor is designed for the smallest possible logic size while still providing adequate performance.

The default options for the Nios® II processor were chosen for these benchmarks, unless specified otherwise.

Note: Results may vary slightly depending on the version of the Intel® Quartus® Prime software, the version of the Nios® II processor, compiler version, target device and the configuration of the processor. Also, any changes to the system logic design might change the performance and LE usage. All results are generated from designs built using the Platform Designer tool.

The Dhrystone MIPS (DMIPS) reports were obtained using the Dhrystone 2.1 benchmark. You can download the Dhrystone 2.1 benchmark software with the Fast Nios® II Hardware Design Example on the Intel FPGA website. For more information about the Dhrystone 2.1 benchmark software and the Fast design example, refer to the readme.txt file which is included in the design example page.

The CoreMark software can be registered and downloaded at www.eembc.org.

Note: The Nios® II Classic and Nios® II benchmark data are very similar. The Nios® II processor was used to create the systems which gave the data values reported in this document. Please refer to the older versions of this document for values associated with the Classic cores.

The resource utilization results were generated using moderate Analysis, Synthesis and Fitter settings in the Quartus Prime software. These results represent typical results.

Table 1.  System Configuration for Nios II Performance Benchmarks
Benchmark Nios® II Processor I-Cache D-Cache Other options Peripherals
fmax Nios® II/f 4 Kbytes 2 Kbytes
  • JTAG debug module (default)
  • Hardware multiplier
  • 64 Kbytes On-chip RAM
  • Avalon Memory-Mapped pipeline Bridge
  • JTAG UART
  • Timer
Nios® II/e None None
  • JTAG debug module (default)
  • 64 Kbytes On-chip RAM
  • Avalon Memory-Mapped pipeline Bridge
  • JTAG UART
  • Timer
Logic size Nios® II/f 4 Kbytes 2 Kbytes
  • JTAG debug module (default)
  • Hardware multiplier
  • 64 Kbytes On-chip RAM
  • Avalon Memory-Mapped pipeline Bridge
  • JTAG UART
  • Timer
  • Avalon UART
  • SDRAM controller3
Nios® II/e None None
  • JTAG debug module (default)
  • 64 Kbytes On-chip RAM
  • Avalon Memory-Mapped pipeline Bridge
  • JTAG UART
  • Timer
  • Avalon UART
  • SDRAM controller3
DMIPS Nios® II/f at 100 MHz 4 Kbytes 2 Kbytes
  • JTAG debug module (default)
  • Hardware multiplier
  • 128 Kbytes On-chip RAM
  • JTAG UART
  • Timer
Nios® II/e at 100 MHz - -
  • JTAG debug module (default)
  • 128 Kbytes On-chip RAM
  • JTAG UART
  • Timer
CoreMark2 Nios® II/f at 100 MHz 32 Kbytes 32 Kbytes
  • JTAG debug module (default)
  • Hardware multiplier
  • 128 Kbytes On-chip RAM
  • JTAG UART
  • Timer
Nios® II/e at 100 MHz - -
  • JTAG debug module (default)
  • 128 Kbytes On-chip RAM
  • JTAG UART
  • Timer
1 The Nios® II/s core is only available with the Nios® II Classic soft processor.
2 This benchmark is compiled with the gcc -o3 switch for optimised performance.
3 The RAM controller for the device is based on DDR3 SDRAM Controller with UniPHY. For Intel® Cyclone® 10, Intel® Arria® 10, Intel® Stratix® 10, and Intel® Agilex™ devices, the RAM controller is based on the respective device IP.