Product Collection
MAX® V CPLD
Status
Launched
Launch Date
2010
Lithography
180 nm

Resources

Logic Elements (LE)
2210
Equivalent Macrocells
1700
Pin-to-pin Delay
7 ns
User Flash Memory
8 Kb
Logic Convertible To Memory
Yes

Features

Internal Oscillator
Yes
Fast Power-on Reset
Yes
Boundary-scan JTAG
Yes
JTAG ISP
Yes
Fast Input Registers
Yes
Programmable Register Power-up
Yes
JTAG Translator
Yes
Real-time ISP
Yes
MultiVolt I/Os†
1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5.0 V
I/O Power Banks
4
Maximum Output Enables
271
LVTTL/LVCMOS
Yes
Emulated LVDS Outputs
Yes
32 bit, 66 MHz PCI Compliant
1
Schmitt Triggers
Yes
Programmable Slew Rate
Yes
Programmable Pull-up Resistors
Yes
Programmable GND Pins
Yes
Open-drain Outputs
Yes
Bus Hold
Yes

Package Specifications

Package Options
F256, F324
Package Size
17mm x 17mm, 19mm x 19mm

Supplemental Information

Additional Information