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  1. Nios® V Processor

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Nios® V Processor

Nios® V processors are the next generation of soft processor IPs, designed to bring the power and flexibility of the open-source RISC-V Architecture to FPGA environments. By leveraging the RISC-V instruction set architecture (ISA), the Nios V processors offer scalable solutions that enable a spectrum of applications ranging from simple embedded systems to complex, high-performance applications.

Altera has discontinued the Nios® II IP ordering codes. Refer to PDN 2312 for more information. It is recommended that customers migrate to Nios V.

Read the Nios® V Processor reference manual ›

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New Ashling Visual Studio Code Extension

A flexible development environment with Ashling Visual Studio Code extension

Refer to the user guide

Accelerated Development Setup

  • Intuitive GUI-based debug configuration eliminates complex command-line setups.
  • Auto-detection of devices and cores saves time in project initialization.
  • Seamless CMake integration enables direct import and build of Nios V projects.
  • Quick BSP and application generation support for Nios V.

Comprehensive Debug Capabilities

  • Full runtime debug support for Arm HPS and Nios V cores via USB-Blaster II.
  • Essential debug views (Registers, Memory, Variables, etc.) in one unified interface.
  • Advanced RTOS-aware debugging for FreeRTOS and Zephyr through Embedded Tools.
  • QEMU simulator support for testing without physical hardware.

Enhanced Development Experience

  • Custom instruction support with easy XML file browsing for RISC-V.
  • Flexible source code mapping for distributed development environments.
  • WSL compatibility for Linux development in a Windows environment.
  • Complete visibility into peripheral registers for hardware-software integration.

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Ashling RiscFree IDE

The Ashling RiscFree IDE for Altera® FPGAs is the integrated development environment for creating embedded applications on an Arm*-based hard processor system and Nios V soft processors. This IDE delivers homogenous and heterogeneous multi-processor design, and debug capabilities. Currently, supported key features include:

  • Included with Quartus Prime Software Pro version 22.2 onwards or available as a standalone free download for embedded software developers.
  • Full toolchain, including Ashling RiscFree for Altera FPGAs IDE, Compiler, Debugger, and Trace.
  • IDE based on Eclipse with full source and project creation, editing, build and debug support.
  • Run-time debug with support for the Altera FPGA Download Cable II (USB Blaster II).
  • Register visualization for Nios V processors and Arm cores.
  • Real-Time Operating System (RTOS) debug awareness.

Ashling RiscFree IDE User Guide

Multi-Platform RISC-V Support for Nios V Soft Processor

Read about our partnership with Ashling and how its RiscFree IDE streamlines development and debugging processes for Nios V applications.

Read the white paper

Embedded Operating Systems

Operating System Availability
Intel HAL Shipped in Quartus
uC/OS-II Shipped in Quartus
FreeRTOS Shipped in Quartus
Zephyr Rocketboards.org
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Additional Resources

Find IP

Find the right Altera® FPGA Intellectual Property core for your needs.

Technical Support

For technical support on this IP core, please visit Support Resources or Intel® Premier Support. You may also search for related topics on this function in the Knowledge Center and Communities.

IP Evaluation and Purchase

Evaluation mode and purchasing information for Altera® FPGA Intellectual Property cores.

IP Base Suite

Free Altera® FPGA IP Core licenses with an active license for Quartus® Prime Standard or Pro Edition Software.

Design Examples

Download design examples and reference designs for Altera® FPGA devices.

Contact Sales

Get in touch with sales for your Altera® FPGA product design and acceleration needs.

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