JESD204B Intel® FPGA IP
Intel provides the JESD204B serial interface in the industry across multiple products –from low-cost or low-power to high-performance FPGAs and SoCs. The JESD204B Intel FPGA IP is a high-speed point-to-point serial interface for digital-to-analog (DAC) or analog-to-digital (ADC) converters to transfer data to FPGA devices.
JESD204B Intel® FPGA IP
The JESD204B Intel FPGA IP incorporates:
- Media access control (MAC)—data link layer (DLL) block that controls the link states and character replacement
- Physical layer (PHY) —physical coding sublayer (PCS) and physical media attachment (PMA) block
With our unique implementation of a full transport layer, design engineers no longer need to analyze documentation to integrate or develop a transport layer solution. Intel’s hardware interoperability testing of the JESD204B Intel FPGA Intellectual Property (IP) core with analog-to-digital converter (ADC) and digital-to-analog converter (DAC) vendors, RFICs, and analog front ends also gets you to market faster.
Features
The JESD204B Intel FPGA IP core delivers the following key features:
- Lane rates of up to 12.5 Gbps (characterized and certified to the JESD204B standard), and lane rates up to 19 Gbps (uncharacterized and not certified to the JESD204B standard)
- Runtime reconfiguration of JESD parameters (L, M, F, S, N, K, CS, CF, data rate)
- Base and PHY partitioning for portability
- Subclass 0 operating mode for backward compatibility to JESD204A
- Subclass 1 and 2 operating modes for deterministic latency support between the ADC/DAC and FPGA
- Multidevice synchronization
- Serial lane alignment and monitoring
- Ability to tune latency in IP core
- Transceiver channel sharing for transmitter (TX) and receiver (RX) to optimize transceiver count
- Hardware-validated design examples that include transport layer design
IP Quality Metrics
Basics |
|
|---|---|
Year IP was first released |
2014 |
Latest version of Intel® Quartus® Prime software supported |
18.1 |
Status |
Production |
Deliverables |
|
Customer deliverables include the following:
|
|
Any additional customer deliverables provided with IP |
N/A |
Parameterization GUI allowing end user to configure IP |
Y |
IP core is enabled for Intel FPGA IP Evaluation Mode support |
Y |
Source language |
Verilog and VHDL (at wrapper-level) |
Testbench language |
Verilog |
Software drivers provided |
N |
Driver operating system (OS) support |
N |
Implementation |
|
User interface |
Avalon®-ST (Datapath) and Avalon-MM (CSR) |
IP-XACT metadata |
N |
Verification |
|
Simulators supported |
N/A |
Hardware validated |
Y, on Intel FPGA development kits |
Industry-standard compliance testing performed |
Y |
If Yes, which test(s)? |
Electrical testing |
If Yes, on which Intel FPGA device(s)? |
Intel® Stratix® 10, Intel® Arria® 10, Intel® Cyclone® 10 GX, Arria® V, and Stratix® V |
If Yes, date performed |
N/A |
If No, is it planned? |
N/A |
Interoperability |
|
IP has undergone interoperability testing |
Y |
If yes, on which Intel FPGA device(s) |
Intel Stratix 10, Intel Arria 10, Intel Cyclone 10 GX, Arria V, Stratix V |
Interoperability reports available |
Y |
JESD204B IP Quick Start Video
Intel has performed JESD204B Intel FPGA IP hardware validation with converter devices from the following leading vendors. Download hardware checkout reports listed below.
Analog Devices
Related Links
The JESD204B Intel FPGA IP is supported on the following device families:
Documentation
- JESD204B Intel FPGA IP Core User Guide
- JESD204B IP Core Design Example User Guide
- Implementing analog-to-digital converter Multi-Link Designs with Intel Stratix 10 JESD204B RX IP Core
- Implementing analog-to-digital converter Multi-Link Designs with Intel Arria 10 JESD204B RX IP Core
- Implementing JESD204B IP Core System Reference Design with Nios® II Processor
- Using the JESD204B MegaCore Function in Arria V Devices
Note: Texas Instruments' TSW14J57 and TSW14J56 evaluation modules (EVMs) are designed using Intel Arria 10 FPGAs and Arria V FPGAs respectively. All devices from Texas Instruments supported by the TSW14J57EVM and the TSW14J56EVM have been hardware validated to be compatible with the JESD204B Intel FPGA IP.
Additional Resources
Find IP
Find the right Intel® FPGA Intellectual Property core for your needs.
Technical Support
For technical support on this IP core, please visit Support Resources or Intel® Premier Support. You may also search for related topics on this function in the Knowledge Center and Communities.
IP Evaluation and Purchase
Evaluation mode and purchasing information for Intel® FPGA Intellectual Property cores.
Designing with Intel® FPGA IP
Learn more about designing with Intel® FPGA IP, a large selection of off-the-shelf cores optimized for Intel® FPGAs.
IP Base Suite
Free Intel FPGA IP Core licenses with an active license for Intel® Quartus® Prime Standard or Pro Edition Software.
I-Tested
Intel awards the interoperability-tested or I-Tested certification to verified Intel FPGA IP or Intel FPGA Design Solutions Network member IP cores.
Intel® FPGA Partner IP
Browse catalog of Intel® FPGA partner intellectual property cores in the Intel® Solutions Marketplace.
Design Examples
Download design examples and reference designs for Intel® FPGA devices.
IP Certifications
Intel is committed to providing Intellectual Property cores that work seamlessly with Intel® FPGA tools or interface specifications.
Contact Sales
Get in touch with sales for your Intel® FPGA product design and acceleration needs.
† Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit www.intel.com/benchmarks.
Intel and Quartus are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries.
Product and Performance Information
Retail prices reported as of 27 Jan 2022 04:57:38 GMT