The JESD204B Intel® FPGA IP incorporates:
- Media access control (MAC)—data link layer (DLL) block that controls the link states and character replacement.
- Physical layer (PHY)—physical coding sublayer (PCS) and physical media attachment (PMA) block.
With our unique implementation of a full transport layer, design engineers no longer need to analyze documentation to integrate or develop a transport layer solution. Intel’s hardware interoperability testing of the JESD204B Intel® FPGA Intellectual Property (IP) core with analog-to-digital converter (ADC) and digital-to-analog converter (DAC) vendors, RFICs, and analog front ends also gets you to market faster.