Interlaken Intel® FPGA IP

IP Quality Metrics

Basics

Year IP was first released

2012

First version of Intel Quartus Prime Software supported

16.1

Status

Production

Deliverables

Customer deliverables include the following:

    Design file (encrypted source code or post-synthesis netlist)

    Simulation model for ModelSim*- Intel FPGA Edition

    Timing and/or layout constraints

    Documentation with revision control

Y for all

Any additional customer deliverables provided with IP

Testbench and design examples

Parameterization GUI allowing end user to configure IP

N

IP is enabled for the Intel FPGA IP Evaluation Mode Support

Y

Source language

Verilog

Testbench language

Verilog

Software drivers provided

N

Driver operating system (OS) support

N/A

Implementation

User interface

Avalon ST-like

IP-XACT metadata

N

Verification

Simulators supported

NCSim, ModelSim*, VCS/VCSMX, Xcelium

Hardware validated

Intel Arria 10 FPGA Transceiver Signal Integrity Development Kit,

Intel Stratix 10 FPGA Signal Integrity Development Kit

Intel Agilex F-series Transceiver SoC Development Kit

Industry-standard compliance testing performed

N/A

If Yes, which test(s)?

N/A

If Yes, on which Intel FPGA device(s)?

N/A

If Yes, date performed

N/A

If No, is it planned?

N

Interoperability

IP has undergone interoperability testing

N

If yes, on which Intel FPGA device(s)

 

Interoperability reports available

N