Interlaken Look-Aside Intel® FPGA IP

Interlaken Look-Aside Interconnect Protocol

The Interlaken Look-Aside IP core is suited for coprocessing packet classification typically used for networking applications such as: Quality of service routing, traffic profiling, and firewall functions. The IP's low-latency packet interface, coupled with its efficient data processing capability, enables a high degree of design scalability for emerging network applications.

This IP core includes Intel's technology-leading transceivers:

• Physical medium attachment (PMA)
• Physical coding sublayer (PCS)
• Media access control (MAC) layers.

The PCS and PMA layers are hardened within the Stratix® 10, Arria® 10, Stratix V, and Arria V FPGAs.

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Features

Intel has been a part of the Interlaken Alliance since its inception in 2007 and continues to innovate with new protocol features to provide customers with robust and easy-to-implement Interlaken Look-Aside IP solutions. The Interlaken Look-Aside Intel FPGA IP core offers a wide range of bandwidths up to 300G.

The Interlaken Look-Aside IP core is Interlaken Look-Aside Protocol Definition v1.1 compliant and allows system developers to eliminate the computational bottlenecks associated with older, packet classification methods. Intel also offers customized Interlaken Look-Aside IP solutions. For more information, please contact your local sales representative.

• Data rate selection up to 25 Gbps
• Multi-lane configuration up to 24 lanes
• Packet mode support
• Low-latency transmit and receive datapaths
• BurstShort support: 8 bytes or higher
• Up to two logical channels
• In-band flow control
• Fully integrated IP (MAC, PCS, and PMA layers)
• Tunable pre-emphasis and equalization settings
• Custom IP deliveries available to optimize for various application needs
• Available through the IP catalog in the Quartus® Prime Pro Edition software

Intel and Cavium Team Up to Provide Pre-verified Packet Classification Solution

The Interlaken Look-Aside Intel FPGA IP core on a Stratix® V FPGA with Cavium’s NEURON Search Processor provides customers a proven packet classification solution that can easily be implemented on any networking or data center platform.

To further simplify our customers’ decision-making process, Intel and Cavium have generated an interoperability report that details the various interoperability modes and performance metrics that can be achieved with this complete, high-performance chipset. Contact your sales person for a copy of this report.

Intel and Cavium Connectivity System Overview

IP Status

† Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit www.intel.com/benchmarks. Intel and Quartus are trademarks of Intel Corporation or its subsidiaries in the US and/or other countries.