Interlaken Look-Aside Intel® FPGA IP

Interlaken Look-Aside is a scalable protocol that allows interoperability between a datapath device and a look-aside coprocessor for short, transaction-related transfers. A look-aside coprocessor is connected "to the side" of the datapath, and is not in-line of the main datapath of the switch, router, or other networking device. Interlaken Look-Aside is not directly compatible with Interlaken and can be considered a different operational mode.

Interlaken (2nd Generation) Intel FPGA IP User Guide ›



Interlaken Look-Aside Intel® FPGA IP

System Overview Details
  • Intel: Stratix® V GX device (5SGXMA7)
  • Cavium: NEURON Search processor evaluation board (EBA-NSP)
Interlaken Look-Aside IP configuration setup
  • 4 lanes x 10.3125 Gbps
  • 8 lanes x 10.3125 Gbps
  • Successfully passing traffic reliably using various packet sizes
  • Logical channel processing validated
  • Average latency = 256 nsec (on Intel FPGA ILA IP)
  • Maximum packet throughput = 614 Mpps for packets under 12 bytes
Year IP was first released 2012
Latest version of Intel® Quartus® Prime software supported 20.2
Status Customization Request1

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Timing and/or layout constraints
  • Documentation with revision control
Y for all
Any additional customer deliverables provided with IP Testbench and Design Examples
Parameterization GUI allowing end user to configure IP N
IP core is enabled for the Intel FPGA IP Evaluation Mode Support N
Source language Verilog
Testbench language Verilog
Software drivers provided N
Driver operating system (OS) support N/A
User interface Avalon® ST - like
IP-XACT metadata N
Simulators supported NCSim, ModelSim, VCS/VCSMX, Xcelium
Hardware validated

Y, Intel® Arria® 10 FPGA Transceiver Signal Integrity Development Kit,

Intel® Stratix® 10 FPGA Signal Integrity Development Kit, 

Intel® Agilex™ FPGA F-Series Transceiver-SoC Development Kit

Industry-standard compliance testing performed N/A
If Yes, which test(s)? N/A
If Yes, on which Intel FPGA(s)? N/A
If Yes, date performed N/A
If No, is it planned? N
IP has undergone interoperability testing N
If yes, on which Intel FPGA(s)  
Interoperability reports available  N