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  1. Intel® Products
  2. Intel® FPGA, SoC FPGA and CPLD
  3. Intel® FPGA Intellectual Property
  4. Interface Protocols IP Cores
  5. XAUI PHY Intel® FPGA IP

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XAUI PHY Intel® FPGA IP

The XAUI PHY Intel® FPGA IP core allows you to easily build systems with a very high throughput 10G Ethernet connection. This XAUI PHY along with a 10GbE media access control (MAC) IP core enables an Intel® FPGA to interface to a 10GbE network through a variety of external devices, including a 10GbE PHY device or optical transceiver module.

Read the V-Series Transceiver PHY IP Core user guide ›

Read the Intel® Stratix® 10 L- and H-Tile Transceiver PHY user guide ›

Read the Intel® Arria® 10 Transceiver PHY user guide ›

Read the Intel® Cyclone® 10 GX Transceiver PHY user guide ›

XAUI PHY Intel® FPGA IP

You can implement the XAUI PHY in hard silicon in Intel's 65 nm and 40 nm FPGAs with serial transceivers faster than 3 Gbps. The PHY management functions are implemented in soft IP. In Intel 20 nm and beyond FPGA families, a XAUI PHY can be implemented in soft IP.

Features

  • Complete 10G Ethernet (XAUI) PHY solution for 4X 3.125 Gbps serial external interface
  • PHY consisting of 10GBASE-X physical coding sublayer (PCS), physical medium attachment (PMA), XGMII Extender Sublayer (XGXS), 10G Ethernet (XAUI), and PHY management functions
  • Direct interface with Intel® FPGA 10GbE MAC for a complete solution
  • Direct standard XAUI PHY (4X 3.125 Gbps) connection for chip-to-chip, chip-to-optical module, chip-to-PHY device, backplane, and short cable applications
  • PHY integrated into hard silicon in Intel devices with serial transceivers above 3 Gbps; also soft XAUI PCS available in Stratix® IV, Stratix® V, and Arria® V FPGAs with serial transceivers
  • Dynamic partial reconfigurable I/O (DPRIO) support in serial transceivers to adapt to various XAUI channel characteristics and devices in systems during operation
  • Implementing the Ethernet-standard XAUI PHY functions: data and control bits 8b/10b encoding/decoding and per-lane synchronization, data serialization/deserialization (SERDES) to and from 4X 3.125 Gbps line, receiver four-data lane alignment, deskew, and alignment of four lanes, and receiver rate matching for clock frequency compensation
  • Local serial loopback from transmitter to receiver at the device's serial transceiver for self testing
  • High-performance internal system interfaces
  • Intel® FPGA Avalon® Streaming (Avalon-ST) SDR XGMII, 72 bit at 156.25 Mbps for data transfer
  • Intel® FPGA Avalon® Memory-Mapped (Avalon-MM) 32 bit for agent management

Related Links

Documentation

  • V-Series transceiver PHY IP core user guide
  • Intel® Stratix® 10 L- and H-Tile Transceiver PHY user guide
  • Intel® Arria® 10 Transceiver PHY user guide
  • Intel® Cyclone® 10 GX Transceiver PHY user guide
  • Intel® FPGA IP release notes

Device Support

  • Intel® FPGA IP for ethernet support center
  • Intel® Arria® 10 FPGAs
  • Stratix® V FPGAs
  • Arria® V FPGAs
  • Cyclone® V FPGAs
  • Stratix® II FPGAs
  • Arria® II FPGAs
  • Stratix® IV FPGAs
  • Cyclone® IV FPGAs

Additional Resources

Find IP

Find the right Intel® FPGA Intellectual Property core for your needs.

Technical Support

For technical support on this IP core, please visit Support Resources or Intel® Premier Support. You may also search for related topics on this function in the Knowledge Center and Communities.

IP Evaluation and Purchase

Evaluation mode and purchasing information for Intel® FPGA Intellectual Property cores.

Designing with Intel® FPGA IP

Learn more about designing with Intel® FPGA IP, a large selection of off-the-shelf cores optimized for Intel® FPGAs.

IP Base Suite

Free Intel® FPGA IP Core licenses with an active license for Intel® Quartus® Prime Standard or Pro Edition Software.

Design Examples

Download design examples and reference designs for Intel® FPGA devices.

Contact Sales

Get in touch with sales for your Intel® FPGA product design and acceleration needs.

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