Intel® Cyclone® 10 GX FPGA
Intel® Cyclone® 10 GX FPGA
External Memory Interfaces
Intel® Cyclone® 10 GX devices provide an efficient architecture that allows up to 72 bit wide of DDR3 memory interfaces at up to 1,866 Mbps. This is to support a high level of system bandwidth within the small modular I/O bank structure. The I/Os are designed to provide high-performance support for existing and emerging external memory standards.
Compared to previous generation of Cyclone® FPGAs, the new architecture, and solution provide the following advantages:
- Pre-closed timing in the controller and from the controller to the PHY
- Easier pin placement
For maximum performance and flexibility, the architecture offers hard memory controller and hard PHY for key interfaces.
- The solution offers completely hardened external memory interfaces for several protocols
- The devices feature columns of I/Os that are mixed within the core logic fabric instead of I/O banks on the device periphery
- A single hard Nios® II processor block calibrates all the memory interfaces in an I/O column
- The I/O columns are composed of groups of I/O modules called I/O banks
- Each I/O bank contains a dedicated integer PLL (IO_PLL), hard memory controller, and delay-locked loop
- The PHY clock tree is shorter compared to previous generation Cyclone® devices and only spans one I/O bank
The Nios® II processor family consists of two configurable 32 bit Harvard architecture cores:
- Fast (/f core): Six-stage pipeline optimized for highest performance, optional memory management unit (MMU), or memory protection unit (MPU)
- Economy (/e core): Optimized for smallest size, and available at no cost (no license required)
Need to boost performance? No problem. Hardware acceleration is as easy as using an FPGA's programmable logic to offload and accelerate tasks that are typically implemented in an application software. Find out more on the Nios® II Processor web page.
For more information on free software development tools, visit the Nios® II Processor Design Tools web page.
For Nios® II processor training, visit the Intel® FPGA Technical Training web page.
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