GTS Dynamic Reconfiguration Controller IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 849710
Date 8/11/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Quick Start Guide 3. Configuring and Generating the IP 4. Integrating the GTS Dynamic Reconfiguration Controller IP With Your Application 5. Designing with the IP Core 6. Designing the IP Solution 7. Sharing Clocking and Applying SDC Constraints 8. Runtime Flow 9. Simulating the IP 10. Validating the IP 11. Appendix A: Functional Description 12. Registers 13. Document Revision History for the GTS Dynamic Reconfiguration Controller IP User Guide
1. Overview x
1.1. About the GTS Dynamic Reconfiguration Controller IP 1.2. About the Document 1.3. Key Concepts 1.4. System Level Block Diagram 1.5. Design Checklist 1.6. IP Design Flow 1.7. Dynamic Reconfiguration 1.8. Design Considerations 1.9. Design Migration Guidelines 1.10. Design Flow Requirements
1.1. About the GTS Dynamic Reconfiguration Controller IP x
1.1.1. Release Information 1.1.2. Features 1.1.3. High-Level Functional Overview 1.1.4. Licensing the IP 1.1.5. Device Family Support 1.1.6. Device Speed Grade Support 1.1.7. IP Performance and Resource Utilization
1.2. About the Document x
1.2.1. Target Audience 1.2.2. Conventions Used in the Document 1.2.3. Terminology 1.2.4. Acronyms 1.2.5. Reference Documents and Training 1.2.6. GTS Dynamic Reconfiguration Target Applications
2. Quick Start Guide x
2.1. Steps to Generate and Run the Design Example 2.2. Steps to Create a Custom Dynamic Reconfiguration Design
2.1. Steps to Generate and Run the Design Example x
2.1.1. Generating the Design Example 2.1.2. Compiling the Design Example 2.1.3. Simulating the Design Example 2.1.4. Validating the Design Example
2.2. Steps to Create a Custom Dynamic Reconfiguration Design x
2.2.1. Simulating the Custom Design 2.2.2. Validating the Custom Design
3. Configuring and Generating the IP x
3.1. Configuring the Quartus® Prime Pro Edition Project 3.2. Generating Dynamic Reconfiguration Design and Configuration Profiles 3.3. Generating HDL for Synthesis and Simulation 3.4. Using the Dynamic Reconfiguration Assignment Editor 3.5. Generating HSSI Dynamic Reconfiguration IP 3.6. Generating the Design Example 3.7. Compiling the Design Example
3.2. Generating Dynamic Reconfiguration Design and Configuration Profiles x
3.2.1. Configuring the IP
3.2.1. Configuring the IP x
3.2.1.1. Configuring the IP Presets 3.2.1.2. Configuring the IP Parameters
3.4. Using the Dynamic Reconfiguration Assignment Editor x
3.4.1. Quartus User Flow
3.4.1. Quartus User Flow x
3.4.1.1. IP List 3.4.1.2. Dynamic Reconfiguration Group List 3.4.1.3. Properties 3.4.1.4. DR Group Visualization Pane 3.4.1.5. Messages Pane
3.6. Generating the Design Example x
3.6.1. Generated Directory Structure and Files
4. Integrating the GTS Dynamic Reconfiguration Controller IP With Your Application x
4.1. High-Level Interface Types 4.2. Dependent/Supporting IPs 4.3. Implementing Required Clocking 4.4. Implementing Required Resets 4.5. Implementing Required AVMM Interface 4.6. Control and Status Interface 4.7. Implementing Mux Selector Interface 4.8. Implementing SRC Interface 4.9. Implementing Local AVMM Interface 4.10. Connecting the Interfaces 4.11. Signal Functions 4.12. Integrating the IP With User Logic 4.13. Integrating the IP With Your Board 4.14. Integrating the IP on the Stack With a Software Driver
5. Designing with the IP Core x
5.1. Release Constraints 5.2. DR Design Guidelines
6. Designing the IP Solution x
6.1. Dynamic Reconfiguration QSF Settings 6.2. Defining DR Combinations 6.3. Instantiating the Generated DR Group 6.4. Generating and Instantiating the DR Controller
9. Simulating the IP x
9.1. Design Example Features 9.2. Simulating the GTS PMA/FEC Direct PHY Altera FPGA IP Example Design Testbench 9.3. Simulating the Ethernet to CPRI Dynamic Reconfiguration Altera FPGA IP Design Example Testbench
9.2. Simulating the GTS PMA/FEC Direct PHY Altera FPGA IP Example Design Testbench x
9.2.1. Simulating the Design Example
9.2.1. Simulating the Design Example x
9.2.1.1. Simulating the Testbench Flow 9.2.1.2. Verifying the Simulation Results
9.3. Simulating the Ethernet to CPRI Dynamic Reconfiguration Altera FPGA IP Design Example Testbench x
9.3.1. Simulating the Design Example
9.3.1. Simulating the Design Example x
9.3.1.1. Verifying the Simulation Results
10. Validating the IP x
10.1. List of Switches on the Developer Kit 10.2. Testing the Hardware Design Example for PMA Direct PHY Multirate 10.3. Testing the Hardware Design Example for Ethernet to CPRI 10.4. Troubleshooting and Debugging Issues
10.2. Testing the Hardware Design Example for PMA Direct PHY Multirate x
10.2.1. Configure the Clocks in Hardware 10.2.2. Program the FPGA 10.2.3. Running the Hardware Test
10.3. Testing the Hardware Design Example for Ethernet to CPRI x
10.3.1. Running the Hardware Test
11. Appendix A: Functional Description x
11.1. AVMM Clock Crossing Bridge 11.2. AVMM Decoder 11.3. Mux Sel, Local AVMM, and SRC Interface 11.4. Dynamic Reconfiguration CSR
12. Registers x
12.1. Configuration Registers 12.2. GTS Transceiver PHY Design Example: Registers 12.3. Ethernet to CPRI Design Example: Registers
12.1. Configuration Registers x
12.1.1. Register Next ID Configuration 0 12.1.2. Register Next ID Configuration 1 12.1.3. Register Next ID Configuration 2 12.1.4. Register Next ID Configuration 3 12.1.5. Register Next ID Configuration 4 12.1.6. Register Next ID Configuration 5 12.1.7. Register Next ID Configuration 6 12.1.8. Register Next ID Configuration 7 12.1.9. Register Next ID Configuration 8 12.1.10. Register Next ID Configuration 9 12.1.11. Register Next ID Configuration 10 12.1.12. Register Next ID Configuration 11 12.1.13. Register Next ID Configuration 12 12.1.14. Register Next ID Configuration 13 12.1.15. Register Next ID Configuration 14 12.1.16. Register Next ID Configuration 15 12.1.17. Register Next ID Configuration 16 12.1.18. Register Next ID Configuration 17 12.1.19. Register Next ID Configuration 18 12.1.20. Register Next ID Configuration 19 12.1.21. Register Trigger 12.1.22. Register Trigger Status 12.1.23. Register Error Configuration 12.1.24. Register Error Status
1. Overview
2. Quick Start Guide
3. Configuring and Generating the IP
4. Integrating the GTS Dynamic Reconfiguration Controller IP With Your Application
5. Designing with the IP Core
6. Designing the IP Solution
7. Sharing Clocking and Applying SDC Constraints
8. Runtime Flow
9. Simulating the IP
10. Validating the IP
11. Appendix A: Functional Description
12. Registers
13. Document Revision History for the GTS Dynamic Reconfiguration Controller IP User Guide

3.6.1. Generated Directory Structure and Files

The GTS Dynamic Reconfiguration Controller IP contains the following generated files for testbench, simulation, and hardware design example files.
Figure 21. Directory Structure for GTS Dynamic Reconfiguration Controller IP Design Example
Table 17.  Testbench File Descriptions for Design Example
Directory/File Description
Key Testbench and Simulation Files for DPHY (PMA/FEC Direct) Designs
<design_example_dir>/example_testbench/gts_dphy_dr_ed_hw.qsf Quartus® Prime setting file.
<design_example_dir>/example_testbench/basic_avl_tb.top.sv Top-level testbench file. The testbench instantiates the DUT wrapper and runs verilog HDL tasks to generate and accept packets.
<design_example_dir>/hardware_test_design/gts_dphy_dr_ed_hw.sv DUT wrapper that instantiates DUT and packet client testbench components.
<design_example_dir>/example_testbench/common Hardware design example support files
<design_example_dir>/example_testbench/run_riviera.do Simulation script file for Riviera-PRO* simulator.
Note: Design example for CPRI to Ethernet is not supported on Riviera-PRO* .
<design_example_dir>/example_testbench/run_vsim.do Simulation script file for QuestaSim* simulator.
<design_example_dir>/example_testbench/run_xcelium.do Simulation script file for Xcelium* Simulator.
Note: Design example for CPRI to Ethernet is not supported on Xcelium* .
<design_example_dir>/example_testbench/run_ncsim.do Simulation script file for Cadence NCSim Simulator.
Key Testbench and Simulation Files for Ethernet to CPRI Multirate Designs
<design_example_dir>/example_testbench/basic_avl_tb_top.sv Top-level testbench file. The testbench instantiates the DUT wrapper and runs Verilog HDL tasks to generate and accept packets.
<design_example_dir>/example_testbench/combo_dr_ed_dut.sv Top wrapper that instantiates Ethernet and CPRI PHY Multirate DUT and other testbench components.
Table 18.  Hardware Design Example File Descriptions
File Names Description
Key Hardware Test Design Files for DPHY (PMA/FEC Direct) Example Design
<design_example_dir>/hardware_test_design/gts_dphy_dr_ed_hw.qpf Quartus® Prime project file.
<design_example_dir>/hardware_test_design/gts_dphy_dr_ed_hw.qsf Quartus® Prime project settings file.
<design_example_dir>/hardware_test_design/gts_dphy_dr_ed_hw.sdc Synopsys Design Constraints file. You can copy and modify this file for your own Agilex™ 5 device.
<design_example_dir>/hardware_test_design/gts_dphy_dr_ed_hw.sv Top hardware design file. This file instantiates DUT, JTAG, AVMM, Reset release IP and test CSR.
<design_example_dir>/hardware_test_design/hwtest/main_script.tcl Main script to run hardware test using the system console.
<design_example_dir>/hardware_test_design/hwtest/src/parameter.tcl Stores the configurable variables of the test script. JTAG ID, desired dynamic reconfiguration sequences of the test can be modified through the variables in this file.
For Ethernet to CPRI Multirate Designs
<design_example_dir>/example_testbench/combo_gts_hw.qpf Altera Quartus Prime project file for simulation. You need to compile this project to generate the DR simulation file (dr_top.sv, mif file) at the proper location for simulation.
<design_example_dir>/hardware_test_design/combo_gts_hw.qsf Altera Quartus Prime project file for hardware. You need to compile this project to generate the DR hardware file (dr_top.sv, mif file) at the proper location for hardware.
<design_example_dir>/example_testbench/combo_gts_hw.qsf Altera Quartus Prime project settings file.
<design_example_dir>/hardware_test_design/combo_gts_hw.qsf Altera Quartus Prime project settings file.
<design_example_dir>/hardware_test_design/combo_gts_hw.sv

Top hardware design file. This file instantiates the GTS Combo Ethernet to CPRI Dynamic Reconfiguration DUT Wrapper and Control and Status Interface.
<design_example_dir>/hardware_test_design/combo_dr_ed_csr.sv Combo Ethernet to CPRI Dynamic Reconfiguration Control and Status Interface Wrapper.
<design_example_dir>/hardware_test_design/combo_gts_hw.sdc Synopsys Design Constraints file. You can copy and modify this file for your own GTS device.
common_files_list.f CPRI data generation and checker RTL file list.
<design_example_dir>/hardware_test_design/hwtest/main_script.tcl Main file for accessing System Console.
<design_example_dir>/hardware_test_design/hwtest/src/parameter.tcl Stores the configurable variables of the test script. The JTAG ID and the desired dynamic reconfiguration sequences for the test can be modified through the variables in this file.
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