Power Management User Guide: Agilex™ 3 FPGAs and SoCs

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ID 846855
Date 8/11/2025
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 3 Power Management Overview 2. Agilex™ 3 Power Basics 3. Agilex™ 3 Power and I/O State Sequencing 4. Agilex™ 3 Sensor Monitoring System 5. Agilex™ 3 Power Optimization Techniques and Features 6. Document Revision History for the Power Management User Guide: Agilex™ 3 FPGAs and SoCs
1. Agilex™ 3 Power Management Overview x
1.1. Power System Design Phases 1.2. Power Supplies
1.1. Power System Design Phases x
1.1.1. Choosing a Power Tree 1.1.2. Power Estimation 1.1.3. Power Optimization 1.1.4. Power Generation
2. Agilex™ 3 Power Basics x
2.1. Power Consumption 2.2. Power Estimation Basics 2.3. Power and Thermal Calculator 2.4. Power Analyzer
3. Agilex™ 3 Power and I/O State Sequencing x
3.1. Overview 3.2. Power-Up Sequence Requirements 3.3. Floating Voltage 3.4. Power-On Reset
3.2. Power-Up Sequence Requirements x
3.2.1. Guidelines for I/O Pins in HSIO, HVIO, HPS IO, and SDM IO Banks During Power Sequencing
3.4. Power-On Reset x
3.4.1. Power Supplies Monitored by the POR Circuitry
4. Agilex™ 3 Sensor Monitoring System x
4.1. Voltage Monitoring System 4.2. Temperature Monitoring System 4.3. Sensors Design Considerations
4.1. Voltage Monitoring System x
4.1.1. Voltage Sensor Transfer Function 4.1.2. Voltage Sensor Voltage Reference Pins
4.2. Temperature Monitoring System x
4.2.1. Local Temperature Sensor 4.2.2. Remote Temperature Sensing Diode 4.2.3. Temperature Sensor Locations 4.2.4. Retrieving Local Temperature Sensor Reading 4.2.5. Temperature Sensor Error Codes
4.3. Sensors Design Considerations x
4.3.1. Voltage Monitor Design Guidelines 4.3.2. Guidelines: Connecting External Reference to the Agilex™ 3 Voltage Reference Pins 4.3.3. Temperature Monitor Design Guidelines 4.3.4. Guidelines: Calibrate Temperature Sensing Chip Interfacing the Agilex™ 3 Remote TSD
5. Agilex™ 3 Power Optimization Techniques and Features x
5.1. DSP and M20K Power Gating 5.2. Clock Gating 5.3. Power Sense Line 5.4. Power Optimization Techniques in the Quartus® Prime Software
1. Agilex™ 3 Power Management Overview
2. Agilex™ 3 Power Basics
3. Agilex™ 3 Power and I/O State Sequencing
4. Agilex™ 3 Sensor Monitoring System
5. Agilex™ 3 Power Optimization Techniques and Features
6. Document Revision History for the Power Management User Guide: Agilex™ 3 FPGAs and SoCs

5.1. DSP and M20K Power Gating

Agilex™ 3 devices support power gating for both DSP blocks and M20K memory blocks. By default, the Quartus® Prime software automatically configures unused DSP blocks and M20K memory blocks to be power gated.
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