Performance Monitor (PMON) FPGA IP Release Notes: Agilex™ 3, Agilex™ 5, and Agilex™ 7 FPGAs
1.3. Performance Monitor IP v3.0.0
| Description | Impact |
|---|---|
| Updated width for the CSR address space. | The axilite axaddr port width has been changed to 9. This can only be seen when the Export JTAG parameter is disabled |
| Added minimum filter to the counter metrics. | Allows for user to use the minimum filter through a combination of the Max and Invert filters |
| Added Advanced Latency IP GUI top-level parameter. | The Advanced Latency mode parameter has been enabled for per transaction latency metrics. |
| Added Full Latency configuration to the PMON Configuration library. | The system console library has been updated with the Full Latency (full_lat) configuration. |
Note: This documentation is preliminary and subject to change.