Performance Monitor (PMON) FPGA IP Release Notes: Agilex™ 3, Agilex™ 5, and Agilex™ 7 FPGAs
1.4. Performance Monitor IP v2.0.0
| Description | Impact |
|---|---|
| Bug fixes implemented for the Write Data Width and Read Data Width parameters. | There was an issue with the Write Data Width and Read Data Width respective XUSER bus being exported with width of 1 for values of powers of 2. This issue has been fixed. |
| Added Counter Width IP GUI top-level parameter. | The Counter Width parameter has been enabled to the AXI4 Monitor to allow for smaller PMON variants to be built. |
Note: This documentation is preliminary and subject to change.