1. GTS JESD204B IP Quick Reference
2. About the GTS JESD204B Intel® FPGA IP
3. Getting Started
4. GTS JESD204B IP Functional Description
5. GTS JESD204B IP Deterministic Latency Implementation Guidelines
6. GTS JESD204B IP Debug Guidelines
7. Document Revision History for the GTS JESD204B User Guide
3.1. Introduction to Intel® FPGA IP Cores
3.2. Installing and Licensing Intel® FPGA IP Cores
3.3. Intel® FPGA IP Evaluation Mode
3.4. Upgrading IP Cores
3.5. IP Catalog and Parameter Editor
3.6. Design Walkthrough
3.7. GTS JESD204B IP Design Considerations
3.8. GTS JESD204B IP Parameters
3.9. Analog Parameter Settings
3.10. GTS JESD204B IP Component Files
4.4.1.2. Subclass 1 Operating Mode
The GTS JESD204B IP core maintains a LMFC counter that counts from 0 to (F × K/4)–1 and wraps around again. The LMFC counter resets within two link clock cycles after converter devices issue a common SYSREF frequency to all the transmitters and receivers. The SYSREF frequency must be the same for converter devices that are grouped and synchronized together.
Group | Configuration | SYSREF Frequency |
---|---|---|
ADC Group 1 (2 ADCs) |
|
(6 GHz / 40) / (2 x 16 / 4) = 18.75 MHz |
ADC Group 2 (2 ADCs) |
|
(Data rate / 40) / (F x K / 4)(6 GHz / 40) / (2 x 16 / 4) = 18.75 MHz |
DAC Group 3 (2 DACs) |
|
(3 GHz / 40) / (2 x 16 / 4) = 9.375 MHz |