GTS JESD204B IP User Guide

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ID 832100
Date 10/31/2025
Public
Document Table of Contents
Document Table of Contents x
1. GTS JESD204B IP Quick Reference 2. About the GTS JESD204B IP 3. Getting Started 4. GTS JESD204B IP Functional Description 5. GTS JESD204B IP Deterministic Latency Implementation Guidelines 6. GTS JESD204B IP Debug Guidelines 7. Document Revision History for the GTS JESD204B User Guide
2. About the GTS JESD204B IP x
2.1. Release Information 2.2. Device Family Support 2.3. Datapath Modes 2.4. IP Variation 2.5. GTS JESD204B IP Configuration 2.6. Channel Bonding 2.7. Performance and Resource Utilization
3. Getting Started x
3.1. Introduction to IP Cores 3.2. Installing and Licensing IP Cores 3.3. Altera® FPGA IP Evaluation Mode 3.4. Upgrading IP Cores 3.5. IP Catalog and Parameter Editor 3.6. Design Walkthrough 3.7. GTS JESD204B IP Design Considerations 3.8. GTS JESD204B IP Parameters 3.9. Analog Parameter Settings 3.10. GTS JESD204B IP Component Files
3.6. Design Walkthrough x
3.6.1. Creating a New Quartus® Prime Project 3.6.2. Parameterizing and Generating the IP 3.6.3. Compiling the GTS JESD204B IP Core Design 3.6.4. Programming an FPGA Device
3.7. GTS JESD204B IP Design Considerations x
3.7.1. Integrating the GTS JESD204B IP in Platform Designer 3.7.2. Pin Assignments 3.7.3. Configuring the GTS Reset Sequencer IP 3.7.4. REFCLK Recovery (CLK RX)
4. GTS JESD204B IP Functional Description x
4.1. Transmitter 4.2. Receiver 4.3. Dual Simplex Support 4.4. Operation 4.5. Clocking Scheme 4.6. Reset Scheme 4.7. Signals 4.8. Registers
4.1. Transmitter x
4.1.1. TX Data Link Layer 4.1.2. TX PHY Layer
4.1.1. TX Data Link Layer x
4.1.1.1. TX CGS 4.1.1.2. TX ILAS 4.1.1.3. User Data Phase
4.2. Receiver x
4.2.1. RX Data Link Layer 4.2.2. RX PHY Layer
4.2.1. RX Data Link Layer x
4.2.1.1. RX CGS 4.2.1.2. Frame Synchronization 4.2.1.3. Frame Alignment 4.2.1.4. Lane Alignment 4.2.1.5. ILAS Data 4.2.1.6. Initial Lane Synchronization
4.4. Operation x
4.4.1. Operating Modes 4.4.2. Scrambler/Descrambler 4.4.3. SYNC_N Signal 4.4.4. Link Reinitialization 4.4.5. Link Startup Sequence 4.4.6. Error Reporting Through SYNC_N Signal
4.4.1. Operating Modes x
4.4.1.1. Subclass 0 Operating Mode 4.4.1.2. Subclass 1 Operating Mode 4.4.1.3. Subclass 2 Operating Mode
4.5. Clocking Scheme x
4.5.1. Device Clock 4.5.2. Link Clock 4.5.3. Local MultiFrame Clock 4.5.4. Clock Correlation 4.5.5. GTS Reset Sequencer IP Clock 4.5.6. HVIO PLL Clocking Mode
4.6. Reset Scheme x
4.6.1. Reset Sequence 4.6.2. TX Reset Entry and Exit Sequence 4.6.3. RX Reset Entry and Exit Sequence
4.7. Signals x
4.7.1. Transmitter Signals 4.7.2. Receiver Signals
4.8. Registers x
4.8.1. Register Access Type Convention 4.8.2. Register Map and Definition 4.8.3. Transmitter Registers 4.8.4. Receiver Registers
5. GTS JESD204B IP Deterministic Latency Implementation Guidelines x
5.1. Constraining Incoming SYSREF Signal 5.2. Programmable RBD Offset 5.3. Programmable LMFC Offset 5.4. Maintaining Deterministic Latency during Link Reinitialization
6. GTS JESD204B IP Debug Guidelines x
6.1. Clocking Scheme 6.2. GTS JESD204B Parameters 6.3. SPI Programming 6.4. Converter and FPGA Operating Conditions 6.5. Signal Polarity and FPGA Pin Assignment 6.6. Transceiver Toolkit
1. GTS JESD204B IP Quick Reference
2. About the GTS JESD204B IP
3. Getting Started
4. GTS JESD204B IP Functional Description
5. GTS JESD204B IP Deterministic Latency Implementation Guidelines
6. GTS JESD204B IP Debug Guidelines
7. Document Revision History for the GTS JESD204B User Guide

4.3. Dual Simplex Support

In cases where the TX IP and RX IP use different parameter settings (e.g. data rate, number of lanes L, M, F, S, etc.) or the number of TX and RX channels needed differs, you can use a dual simplex (DS) group to maximize your transceiver channel usage.

For a DS group, you may create an independent simplex TX IP (with one or more channels) and an independent simplex RX IP (with one or more channels) and use the HSSI Support Logic Assignment Editor to fit them into the same transceiver channels. Refer to the GTS Transceiver Dual Simplex Interfaces User Guide for more information.

To create a DS group:
  1. Generate the GTS JESD204B TX and RX simplex IP. You can also create a mixed-IP DS group with Serial Lite IV IP or GTS JESD204C IP ( Agilex™ 5 devices only). There are two possible mixed-IP combinations that can be used:
    • GTS JESD204B IP + GTS Serial Lite IV IP (both Agilex™ 3 and Agilex™ 5)
    • GTS JESD204B IP + GTS JESD204C IP ( Agilex™ 5 only)
    Table 14.  Possible Combinations for TX IP and RX IP in a DS groupEach combination in the table represents a single DS group. It is possible to have multiple DS groups in the design.
    IP Combination TX IP RX IP Supported Clocking Mode

    Single-type IP

    (both Agilex™ 3 and Agilex™ 5)

    		 (a) GTS JESD204B IP GTS JESD204B IP System/HVIO PLL or PMA clocking mode

    Mixed-type IP: JESD204B IP + GTS Serial Lite IV IP

    (both Agilex™ 3 and Agilex™ 5)

    		 (b) GTS JESD204B IP GTS Serial Lite IV IP System/HVIO PLL only
    (c) GTS Serial Lite IV IP GTS JESD204B IP System/HVIO PLL only

    Mixed-type IP: JESD204B IP + GTS JESD204C IP

    ( Agilex™ 5 only)

    		 (d) GTS JESD204B IP GTS JESD204C IP System/HVIO PLL or PMA clocking mode
    (e) GTS JESD204C IP GTS JESD204B IP System/HVIO PLL or PMA clocking mode
    1. Select System/HVIO PLL in the Clocking mode option in IP GUI main tab to allow merging between GTS JESD204B and Serial Lite IV IP ((b) and (c)). When using GTS JESD204B IP only ((a)) or GTS JESD204B IP and GTS JESD204C IP ((d) and (e)) combination in the same DS group, both System/HVIO PLL and PMA clocking modes are supported.
    2. Configure the System/HVIO PLL frequency parameter according to the formula described in GTS JESD204B IP Core Clocks.
    Note:

    The System/HVIO PLL is shared between TX and RX IPs in dual simplex mode. Using different data rates for TX and RX in dual simplex mode will result in having different System/HVIO PLL frequencies required for both TX and RX channels. In this scenario, use the highest frequency calculation for the System/HVIO PLL output. Refer to the GTS Transceiver Dual Simplex Interfaces User Guide for more information on the System/HVIO PLL frequency calculation.

    The reference clock frequency selection should be selected based on the highest System/HVIO PLL frequency. The reference clock frequency is the same for both simplex IPs as they are sharing the same System/HVIO PLL. Configure the TX and RX IP to have the same reference clock in the IP parameter editor. For the GTS JESD204B IP, the reference clock is configured via the PLL/CDR Reference Clock Frequency parameter by selecting the available frequency option. Ensure refclk is also supplied with this frequency at the refclk input of the System/HVIO PLL.

    Note: When creating a DS group with JESD204B and Serial Lite IV, RS-FEC mode must be disabled in the Serial Lite IV IP.
  2. Provide location of each simplex IP in a DS group relative to the starting channel location in the HSSI Support Logic Assignment Editor. To do this, open the HSSI Support Logic Assignment Editor in Quartus® Prime by selecting Assignments > HSSI Support Logic Assignment Editor.
  3. Assign your individual simplex IPs to a dual simplex (DS) group by right-clicking your IP component under the IP > Click Create Instance in… > Select or create a new DS group.
    Figure 11. HSSI Support Logic Assignment Editor

    The HSSI Support Logic Assignment Editor does a quick legality check (protocol level and attribute level) to see if the simplex IPs assigned to a dual simplex group are compatible. If the simplex IPs are not compatible, error messages will be prompted.

  4. After assigning simplex IPs to a DS group, save the assignments. When you save the DS group, the QSF assignments are added automatically to the project QSF. For example:
  5. Run the HSSI Dual Simplex IP Generation in the Compilation Dashboard to obtain a new DS IP:
  6. Connect the generated DS IP to the rest of your design logic:

    This DS IP (DS_GROUP_0) contains the ports of both the TX and RX simplex IPs created in step 1 in a single module. It also merges the ports associated with the reset sequencer and System/HVIO PLL (if used) in the same module.

    You can now instantiate this module in your design. You may obtain the instantiation template of DS_GROUP_0 in the following files:

    • Verilog: <Quartus project folder>/DS_GROUP_0/DS_GROUP_0_inst.v
    • VHDL: <Quartus project folder>/DS_GROUP_0/DS_GROUP_0_inst.vhd

    Perform the required connections. If you have selected System PLL clocking mode earlier, connect the output of the System PLL to the sysclk port of the DS_GROUP_0 module. If you have selected HVIO PLL clocking mode, connect the output outclk_0 and locked signals of the HVIO PLL to the sysclk and syspll_locked ports of the DS_GROUP_0 module respectively.

    Refer to the GTS Transceiver Dual Simplex Interfaces User Guide for more info on performing the connections.

Note:

The Dual Simplex support for the GTS JESD204B IP in current release of the Quartus® Prime software is limited to:

  • A DS group can only contain one Simplex TX IP (JESD204B/JESD204C/Serial Lite IV) and one Simplex RX IP (JESD204B/JESD204C/Serial Lite IV).
  • Simulation and hardware supports up to L=4 only.
  • Refclk recovery (Clkrx) feature is not supported in dual simplex mode for this release.
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