1. GTS JESD204B IP Quick Reference
2. About the GTS JESD204B Intel® FPGA IP
3. Getting Started
4. GTS JESD204B IP Functional Description
5. GTS JESD204B IP Deterministic Latency Implementation Guidelines
6. GTS JESD204B IP Debug Guidelines
7. Document Revision History for the GTS JESD204B Intel® FPGA IP User Guide
3.1. Introduction to Intel® FPGA IP Cores
3.2. Installing and Licensing Intel® FPGA IP Cores
3.3. Intel® FPGA IP Evaluation Mode
3.4. Upgrading IP Cores
3.5. IP Catalog and Parameter Editor
3.6. Design Walkthrough
3.7. GTS JESD204B IP Design Considerations
3.8. GTS JESD204B Intel® FPGA IP Parameters
3.9. Analog Parameter Settings
3.10. GTS JESD204B IP Component Files
3.7.3. Configuring the GTS Reset Sequencer Intel® FPGA IP
In an Agilex™ 5 and Agilex™ 3 device, there is a new requirement to instantiate the GTS Reset Sequencer Intel® FPGA IP for proper transceiver reset operation. This IP can be found in the IP catalog and is required to be instantiated only once for each side of the device. Ensure to select the number of Lane parameter according to the total number of channels used for the particular side of the device this reset sequencer IP is instantiated for.
Note: For more information on connecting the GTS Reset Sequencer Intel® FPGA IP, refer to the Implementing the GTS Reset Sequencer Intel® FPGA IP section in the GTS Transceiver PHY User Guide.