1. GTS JESD204B IP Quick Reference
2. About the GTS JESD204B Intel® FPGA IP
3. Getting Started
4. GTS JESD204B IP Functional Description
5. GTS JESD204B IP Deterministic Latency Implementation Guidelines
6. GTS JESD204B IP Debug Guidelines
7. Document Revision History for the GTS JESD204B Intel® FPGA IP User Guide
3.1. Introduction to Intel® FPGA IP Cores
3.2. Installing and Licensing Intel® FPGA IP Cores
3.3. Intel® FPGA IP Evaluation Mode
3.4. Upgrading IP Cores
3.5. IP Catalog and Parameter Editor
3.6. Design Walkthrough
3.7. GTS JESD204B IP Design Considerations
3.8. GTS JESD204B Intel® FPGA IP Parameters
3.9. Analog Parameter Settings
3.10. GTS JESD204B IP Component Files
3.9. Analog Parameter Settings
A Graphical User Interface (GUI) is provided to set the analog parameters of the GTS PMAs. These settings are required to ensure the functionality of the design on hardware.
Refer to the Analog Parameter Options section in the GTS Transceiver PHY User Guide for more information.