GTS JESD204B IP User Guide

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ID 832100
Date 8/29/2025
Public
Document Table of Contents
Document Table of Contents x
1. GTS JESD204B IP Quick Reference 2. About the GTS JESD204B Intel® FPGA IP 3. Getting Started 4. GTS JESD204B IP Functional Description 5. GTS JESD204B IP Deterministic Latency Implementation Guidelines 6. GTS JESD204B IP Debug Guidelines 7. Document Revision History for the GTS JESD204B User Guide
2. About the GTS JESD204B Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. Datapath Modes 2.4. IP Variation 2.5. GTS JESD204B IP Configuration 2.6. Channel Bonding 2.7. Performance and Resource Utilization
3. Getting Started x
3.1. Introduction to Intel® FPGA IP Cores 3.2. Installing and Licensing Intel® FPGA IP Cores 3.3. Intel® FPGA IP Evaluation Mode 3.4. Upgrading IP Cores 3.5. IP Catalog and Parameter Editor 3.6. Design Walkthrough 3.7. GTS JESD204B IP Design Considerations 3.8. GTS JESD204B IP Parameters 3.9. Analog Parameter Settings 3.10. GTS JESD204B IP Component Files
3.6. Design Walkthrough x
3.6.1. Creating a New Quartus® Prime Project 3.6.2. Parameterizing and Generating the IP 3.6.3. Compiling the GTS JESD204B IP Core Design 3.6.4. Programming an FPGA Device
3.7. GTS JESD204B IP Design Considerations x
3.7.1. Integrating the GTS JESD204B IP in Platform Designer 3.7.2. Pin Assignments 3.7.3. Configuring the GTS Reset Sequencer Intel® FPGA IP
4. GTS JESD204B IP Functional Description x
4.1. Transmitter 4.2. Receiver 4.3. Dual Simplex Support 4.4. Operation 4.5. Clocking Scheme 4.6. Reset Scheme 4.7. Signals 4.8. Registers
4.1. Transmitter x
4.1.1. TX Data Link Layer 4.1.2. TX PHY Layer
4.1.1. TX Data Link Layer x
4.1.1.1. TX CGS 4.1.1.2. TX ILAS 4.1.1.3. User Data Phase
4.2. Receiver x
4.2.1. RX Data Link Layer 4.2.2. RX PHY Layer
4.2.1. RX Data Link Layer x
4.2.1.1. RX CGS 4.2.1.2. Frame Synchronization 4.2.1.3. Frame Alignment 4.2.1.4. Lane Alignment 4.2.1.5. ILAS Data 4.2.1.6. Initial Lane Synchronization
4.4. Operation x
4.4.1. Operating Modes 4.4.2. Scrambler/Descrambler 4.4.3. SYNC_N Signal 4.4.4. Link Reinitialization 4.4.5. Link Startup Sequence 4.4.6. Error Reporting Through SYNC_N Signal
4.4.1. Operating Modes x
4.4.1.1. Subclass 0 Operating Mode 4.4.1.2. Subclass 1 Operating Mode 4.4.1.3. Subclass 2 Operating Mode
4.5. Clocking Scheme x
4.5.1. Device Clock 4.5.2. Link Clock 4.5.3. Local MultiFrame Clock 4.5.4. Clock Correlation 4.5.5. GTS Reset Sequencer Intel® FPGA IP Clock
4.6. Reset Scheme x
4.6.1. Reset Sequence 4.6.2. TX Reset Entry and Exit Sequence 4.6.3. RX Reset Entry and Exit Sequence
4.7. Signals x
4.7.1. Transmitter Signals 4.7.2. Receiver Signals
4.8. Registers x
4.8.1. Register Access Type Convention 4.8.2. Register Map and Definition 4.8.3. Transmitter Registers 4.8.4. Receiver Registers
5. GTS JESD204B IP Deterministic Latency Implementation Guidelines x
5.1. Constraining Incoming SYSREF Signal 5.2. Programmable RBD Offset 5.3. Programmable LMFC Offset 5.4. Maintaining Deterministic Latency during Link Reinitialization
6. GTS JESD204B IP Debug Guidelines x
6.1. Clocking Scheme 6.2. GTS JESD204B Parameters 6.3. SPI Programming 6.4. Converter and FPGA Operating Conditions 6.5. Signal Polarity and FPGA Pin Assignment 6.6. Transceiver Toolkit
1. GTS JESD204B IP Quick Reference
2. About the GTS JESD204B Intel® FPGA IP
3. Getting Started
4. GTS JESD204B IP Functional Description
5. GTS JESD204B IP Deterministic Latency Implementation Guidelines
6. GTS JESD204B IP Debug Guidelines
7. Document Revision History for the GTS JESD204B User Guide

4.6.2. TX Reset Entry and Exit Sequence

Figure 19. TX IP Reset Entry and Exit Sequence

The descriptions below correspond to Figure 19:

  1. The user logic asserts the GTS JESD204B IP and configuration reset to the GTS JESD204B IP TX, jesd204_tx_avs_rst_n = 0, jesd204_tx_rst_n = 0, and reconfig_xcvr_reset = 1.
    Note: If you assert jesd204_tx_avs_rst_n and reconfig_xcvr_reset, jesd204_tx_rst_n is required to be asserted as well. You can opt to assert jesd204_tx_rst_n without asserting jesd204_tx_avs_rst_n and reconfig_xcvr_reset.
  2. Wait for the Core PLL to lock. After which, the user logic deasserts jesd204_tx_avs_rst_n and reconfig_xcvr_reset and perform configurations of the PHY and IP.
  3. After all relevant PHY channels are fully in reset, the IP core asserts jesd204_tx_rst_ack_n = 0 to the user logic. Knowing the relevant channels are in proper reset states, the user logic can release the reset to the IP core when possible (jesd204_tx_rst_n = 1). Use jesd204_tx_rst_ack_n as an indicator to deassert jesd204_tx_rst_n = 1.
  4. The user logic deasserts the IP reset (jesd204_tx_rst_n = 1).
  5. The IP core deasserts jesd204_tx_rst_ack_n = 1 to indicate that reset sequence is complete.
  6. The IP core asserts jesd204_tx_out_of_reset = 1 to user. You must synchronize jesd204_tx_out_of_reset to rxlink_clk or rxframe_clk domain before use.
  7. For Subclass 1, if the continuous SYSREF pulses from the clock generator are present when the TX link reset is deasserted, the TX link initializes. If the SYSREF pulse is not present, trigger the clock generator to provide a SYSREF pulse to initialize the link after jesd204_tx_out_of_reset = 1.
  8. When the IP is ready to receive data from the application, the IP core assert jesd204_tx_frame_ready = 1 and jesd204_tx_link_ready = 1 to user. The GTS JESD204B TX IP Core is operational.
  9. At any time when you require a reset to the MAC and PHY, you must wait for jesd204_tx_rst_ack_n = 1. Assertion of jesd204_tx_rst_n = 0 resets the MAC and PHY in the IP core.
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