1. GTS JESD204B IP Quick Reference
2. About the GTS JESD204B Intel® FPGA IP
3. Getting Started
4. GTS JESD204B IP Functional Description
5. GTS JESD204B IP Deterministic Latency Implementation Guidelines
6. GTS JESD204B IP Debug Guidelines
7. Document Revision History for the GTS JESD204B User Guide
3.1. Introduction to Intel® FPGA IP Cores
3.2. Installing and Licensing Intel® FPGA IP Cores
3.3. Intel® FPGA IP Evaluation Mode
3.4. Upgrading IP Cores
3.5. IP Catalog and Parameter Editor
3.6. Design Walkthrough
3.7. GTS JESD204B IP Design Considerations
3.8. GTS JESD204B IP Parameters
3.9. Analog Parameter Settings
3.10. GTS JESD204B IP Component Files
5. GTS JESD204B IP Deterministic Latency Implementation Guidelines
Subclass 1 and Subclass 2 modes support deterministic latency. This section describes the features available in the GTS JESD204B IP that you can use to achieve Subclass 1 deterministic latency in your design. This section also covers some best practices for Subclass 1 implementation like constraining the incoming SYSREF signal and maintaining deterministic latency during link reinitialization.
Features available:
- Programmable RBD offset.
- Programmable LMFC offset.