2.3. Step 3: Using the JTAG Debug Service
Follow these steps to exercise the JTAG DEBUG service path that the JTAG master component provides:
- To locate the JTAG DEBUG service path of the JTAG master, and save that path to a new jd_path Tcl variable, type the following command:
set jd_path [lindex [get_service_paths jtag_debug] 0]
- To exercise the JTAG interface by sending a list of values through a loopback at TDI and TDO of a system-level debug (SLD) node, type the following command and observe the values returned. This command checks the physical interface of the board and the JTAG TAP controller pins of the FPGA device.
jtag_debug_loop $jd_path [list 1 2 4 8 15 16]
- To check the clock connected to the JTAG master component in the Platform Designer system, type the following command. This command senses whether the clock is active (1) or inactive (0).
jtag_debug_sense_clock $jd_path
- To sample the “state” of the JTAG master component clock, use the following command. To repeatedly sample the clock until capturing both the high (1) and low (0) states, continue pressing the Up Arrow key followed by the Enter key.
jtag_debug_sample_clock $jd_path