GTS SDI II IP User Guide

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ID 823539
Date 10/30/2025
Public
Document Table of Contents
Document Table of Contents x
1. GTS SDI II IP Quick Reference 2. GTS SDI II IP Overview 3. GTS SDI II IP Core Getting Started 4. GTS SDI II IP Parameters 5. GTS SDI II IP Core Functional Description 6. GTS SDI II IP Core Signals 7. GTS SDI II IP Core Design Considerations 8. Design Limitations and Known Issues 9. GTS SDI II IP Core Testbench and Design Examples 10. Document Revision History for the GTS SDI II IP User Guide
2. GTS SDI II IP Overview x
2.1. GTS SDI II Release Information 2.2. GTS SDI II IP Device Family Support 2.3. GTS SDI II IP General Description 2.4. Performance and Resource Utilization
3. GTS SDI II IP Core Getting Started x
3.1. Installing and Licensing IPs 3.2. Design Walkthrough 3.3. GTS SDI II IP Core Component Files 3.4. Compiling the GTS SDI II IP Core Design 3.5. Programming an FPGA
3.1. Installing and Licensing IPs x
3.1.1. IP Evaluation Mode
3.2. Design Walkthrough x
3.2.1. Creating a New Quartus® Prime Project 3.2.2. Launching IP Catalog 3.2.3. Parameterizing the IP Core 3.2.4. Generating a Design Example and Simulation Testbench
5. GTS SDI II IP Core Functional Description x
5.1. Protocol 5.2. Transceiver 5.3. Submodules 5.4. Optional Features
5.1. Protocol x
5.1.1. Transmitter 5.1.2. Receiver
5.3. Submodules x
5.3.1. Insert Line 5.3.2. Insert/Check CRC 5.3.3. Insert Payload ID 5.3.4. Match TRS 5.3.5. Scrambler 5.3.6. TX Sample 5.3.7. Clock Enable Generator 5.3.8. RX Sample 5.3.9. Detect Video Standard 5.3.10. Detect 1 and 1/1.001 Rates 5.3.11. Transceiver Controller 5.3.12. Descrambler 5.3.13. TRS Aligner 5.3.14. 3Gb Demux 5.3.15. Extract Line 5.3.16. Extract Payload ID 5.3.17. Detect Format 5.3.18. Sync Streams 5.3.19. Convert SD Bits 5.3.20. Insert Sync Bits 5.3.21. Remove Sync Bits
5.4. Optional Features x
5.4.1. SMPTE RP168 Switching Support 5.4.2. SD 20-Bit Interface for Dual/Triple Rate 5.4.3. Intel FPGA Video Streaming Interface
5.4.3. Intel FPGA Video Streaming Interface x
5.4.3.1. RGB Pixel Packing 5.4.3.2. YCbCr 444 Pixel Packing 5.4.3.3. YCbCr 422 Pixel Packing 5.4.3.4. Supported Modes
6. GTS SDI II IP Core Signals x
6.1. GTS SDI II IP Core Resets and Clocks 6.2. Transmitter Protocol Signals 6.3. Receiver Protocol Signals 6.4. Transceiver Signals 6.5. Transmitter Streaming Video and Control Signals 6.6. Receiver Streaming Video and Control Signals
6.2. Transmitter Protocol Signals x
6.2.1. Image Mapping
6.3. Receiver Protocol Signals x
6.3.1. rx_format
7. GTS SDI II IP Core Design Considerations x
7.1. Transceiver Handling Guidelines 7.2. HSSI Support Logic Assignment Editor
7.1. Transceiver Handling Guidelines x
7.1.1. Handling Transceiver in Agilex™ 3 and Agilex™ 5 Devices
7.1.1. Handling Transceiver in Agilex™ 3 and Agilex™ 5 Devices x
7.1.1.1. System PLL Clocking Mode 7.1.1.2. Unused Transceiver Tiles 7.1.1.3. SmartVID Settings
7.2. HSSI Support Logic Assignment Editor x
7.2.1. Using the HSSI Support Logic Assignment Editor
9. GTS SDI II IP Core Testbench and Design Examples x
9.1. Design Examples for Agilex™ 5 Devices
1. GTS SDI II IP Quick Reference
2. GTS SDI II IP Overview
3. GTS SDI II IP Core Getting Started
4. GTS SDI II IP Parameters
5. GTS SDI II IP Core Functional Description
6. GTS SDI II IP Core Signals
7. GTS SDI II IP Core Design Considerations
8. Design Limitations and Known Issues
9. GTS SDI II IP Core Testbench and Design Examples
10. Document Revision History for the GTS SDI II IP User Guide

7.2.1. Using the HSSI Support Logic Assignment Editor

To implement dual simplex or dynamic reconfiguration mode in Agilex™ 3 or Agilex™ 5 devices, you must use the HSSI Support Logic Assignment Editor to create a dual simplex or dynamic reconfiguration group.

To create a dual simplex or dynamic reconfiguration group, you must first create an independent simplex TX IP (with one or more channels) and an independent simplex RX IP (with one or more channels) and subsequently use the HSSI Support Logic Assignment Editor to fit them into the duplex channel.

To create a dual simplex or dynamic reconfiguration group:

  1. Load HSSI Support Logic Assignment Editor, create the instance, and save the assignments. The assignments will be updated in qsf file.
    Note: To use HSSI Support Logic Assignment Editor, you need to run IP Generation first to display the simplex IPs.
  2. Example: Configuring Static Rate (HD, 3G, and 12G) in Dual Simplex Mode with HSSI Support Logic Generation
    1. Add your TX and RX instances to the Dual Simplex Group.
    2. Select sdi_rx_inst0 and sdi_tx_inst0, then create shared clock connections for system_pll_clk and system_pll_lock.
    3. Click the Save Assignments button to save your Dual Simplex Group configuration.
    4. Open your .qsf file to confirm that the following settings are applied.
  3. Example: Configuring Dynamic Reconfiguration (Multi-Rate [up to 12G SDI] and Triple-Rate [up to 3G SDI]) in Dual Simplex Mode with HSSI Support Logic Generation
    1. Add your TX and RX instances to the Dynamic Reconfiguration Group.
    2. Multi-rate—set the reconfigure ID to 5 for sdi_tx_inst and 1 for sdi_rx_inst.
      Note: sdi_rx_inst supports a total of 4 profiles in a multi-rate design.
    3. Triple-rate—set the reconfigure ID to 3 for sdi_tx_inst and 1 for sdi_rx_inst.
      Note: sdi_rx_inst supports a total of 2 profiles in a triple-rate design.
    4. Select sdi_rx_inst and sdi_tx_inst, then create shared clock connections for system_pll_clk and system_pll_lock.
    5. Click the Save Assignments button to save your Dynamic Reconfiguration Group configuration.
    6. Open your .qsf file to confirm that the following settings are applied.
  4. Example: Configuring Dynamic Reconfiguration (Multi-Rate [up to 12G SDI] and Triple-Rate [up to 3G SDI]) with HSSI Support Logic Generation—Non-DS Case
    1. Add your RX instances to the Dynamic Reconfiguration Group.
    2. Multi-rate—set the reconfigure ID to 1 for sdi_rx_inst.
      Note: sdi_rx_inst supports a total of 4 profiles in a multi-rate design.
    3. Triple-rate—set the reconfigure ID to 1 for sdi_rx_inst.
      Note: sdi_rx_inst supports a total of 2 profiles in a triple-rate design.
    4. Click the Save Assignments button to save your Dynamic Reconfiguration Group configuration.
    5. Open your .qsf file to confirm that the following settings are applied.
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