GTS SDI II IP User Guide

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ID 823539
Date 6/30/2025
Public
Document Table of Contents
Document Table of Contents x
1. GTS SDI II IP Quick Reference 2. GTS SDI II IP Core Overview 3. GTS SDI II IP Core Getting Started 4. GTS SDI II IP Parameters 5. GTS SDI II IP Core Functional Description 6. GTS SDI II IP Core Signals 7. GTS SDI II IP Core Design Considerations 8. GTS SDI II IP Core Testbench and Design Examples 9. Document Revision History for the GTS SDI II IP User Guide
2. GTS SDI II IP Core Overview x
2.1. Release Information 2.2. Device Family Support 2.3. General Description 2.4. Performance and Resource Utilization
3. GTS SDI II IP Core Getting Started x
3.1. Installing and Licensing IP Cores 3.2. Design Walkthrough 3.3. GTS SDI II IP Core Component Files 3.4. Compiling the GTS SDI II IP Core Design 3.5. Programming an FPGA
3.1. Installing and Licensing IP Cores x
3.1.1. Intel FPGA IP Evaluation Mode
3.2. Design Walkthrough x
3.2.1. Creating a New Quartus® Prime Project 3.2.2. Launching IP Catalog 3.2.3. Parameterizing the IP Core 3.2.4. Generating a Design Example and Simulation Testbench
5. GTS SDI II IP Core Functional Description x
5.1. Protocol 5.2. Transceiver 5.3. Submodules 5.4. Optional Features
5.1. Protocol x
5.1.1. Transmitter 5.1.2. Receiver
5.3. Submodules x
5.3.1. Insert Line 5.3.2. Insert/Check CRC 5.3.3. Insert Payload ID 5.3.4. Match TRS 5.3.5. Scrambler 5.3.6. TX Sample 5.3.7. Clock Enable Generator 5.3.8. RX Sample 5.3.9. Detect Video Standard 5.3.10. Detect 1 and 1/1.001 Rates 5.3.11. Transceiver Controller 5.3.12. Descrambler 5.3.13. TRS Aligner 5.3.14. 3Gb Demux 5.3.15. Extract Line 5.3.16. Extract Payload ID 5.3.17. Detect Format 5.3.18. Sync Streams 5.3.19. Convert SD Bits 5.3.20. Insert Sync Bits 5.3.21. Remove Sync Bits
5.4. Optional Features x
5.4.1. SMPTE RP168 Switching Support 5.4.2. SD 20-Bit Interface for Dual/Triple Rate 5.4.3. Intel FPGA Video Streaming Interface
5.4.3. Intel FPGA Video Streaming Interface x
5.4.3.1. RGB Pixel Packing 5.4.3.2. YCbCr 444 Pixel Packing 5.4.3.3. YCbCr 422 Pixel Packing 5.4.3.4. Supported Modes
6. GTS SDI II IP Core Signals x
6.1. GTS SDI II IP Core Resets and Clocks 6.2. Transmitter Protocol Signals 6.3. Receiver Protocol Signals 6.4. Transceiver Signals 6.5. Transmitter Streaming Video and Control Signals 6.6. Receiver Streaming Video and Control Signals
6.2. Transmitter Protocol Signals x
6.2.1. Image Mapping
6.3. Receiver Protocol Signals x
6.3.1. rx_format
7. GTS SDI II IP Core Design Considerations x
7.1. Transceiver Handling Guidelines 7.2. Dual Simplex Merging Tool (DS tool)
7.1. Transceiver Handling Guidelines x
7.1.1. Handling Transceiver in Agilex™ 5 Devices
7.1.1. Handling Transceiver in Agilex™ 5 Devices x
7.1.1.1. System PLL Clocking Mode 7.1.1.2. Unused Transceiver Tiles 7.1.1.3. SmartVID Settings
7.2. Dual Simplex Merging Tool (DS tool) x
7.2.1. Using the DS Tool
8. GTS SDI II IP Core Testbench and Design Examples x
8.1. Design Examples for Agilex™ 5 Devices
1. GTS SDI II IP Quick Reference
2. GTS SDI II IP Core Overview
3. GTS SDI II IP Core Getting Started
4. GTS SDI II IP Parameters
5. GTS SDI II IP Core Functional Description
6. GTS SDI II IP Core Signals
7. GTS SDI II IP Core Design Considerations
8. GTS SDI II IP Core Testbench and Design Examples
9. Document Revision History for the GTS SDI II IP User Guide

6.3.1. rx_format

The format represents only the video transport format; not the picture format. For example, when the core transports 1080p50 video on HD-SDI dual link, the video transport format is 1080i50.
Table 18.  Video Format Values
Encoding Value SMPTE Standard Active Lines Per Frame Transport Format Frame Rate
0000 SMPTE ST 259 486 I 29.97
0001 SMPTE ST 259 576 I 25
0100 SMPTE ST 274 1080 I 30/29.97/60/59.9412
0101 SMPTE ST 274 1080 I 25/5013
0110 SMPTE ST 274 1080 P 24/23.98
0111 SMPTE ST 296 720 P 60/59.94
1000 SMPTE ST 296 720 P 50
1001 SMPTE ST 296 720 P 30/29.97
1010 SMPTE ST 296 720 P 25
1011 SMPTE ST 296 720 P 24/23.98
1100 SMPTE ST 274 1080 P 30/29.97/60/59.94
1101 SMPTE ST 274 1080 P 25/50
1110 SMPTE ST 274 1080 I 24
1111 Undetectable format, revert to default value
Others Reserved

To differentiate video format with 1 and 1/1.001 rate, refer to the rx_clkout_is_ntsc_paln output signal. For example, if rx_format = 0100, rx_clkout_is_ntsc_paln = 1, then the format for the received video is 1080i59.94. Otherwise, it is 1080i60.

To differentiate between video format across HD-SDI and 3G-SDI interfaces, also refer to the rx_std output signal. For example, if rx_format = 1100 and rx_clkout_is_ntsc_paln = 0, rx_std = 01, then the received video format is 1080p30. If the rx_std = 11 or 10, then the received video format is 1080p60.
Note: Altera recommends that you refer to the Payload ID to get the most accurate video format details.
For 6G-SDI or 12G-SDI interfaces, each of the 20-bit interface reports its own detected format. For example, rx_format of all four 20-bit interfaces report 1100 (1080p60) when receiving 2160p60 in 12G-SDI, whereas only the lower two interfaces report valid rx_format in 6G-SDI.
Table 19.  Example of 16-bit rx_format for 6G-SDI and 12G-SDI Interfaces
SDI Interface rx_format
[15:11] [11:8] [7:4] [3:0]
12G-SDI 1100 1100 1100 1100
6G-SDI Not valid Not valid 1100 1100
12 Frame rates 60 and 59.94 are meant for 3G Level B/HD Dual Link when receiving 1080p60/59.94 format.
13 Frame rate 50 is meant for 3G Level B/HD Dual Link when receiving 1080p50 format.
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