GTS SDI II IP User Guide

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ID 823539
Date 6/30/2025
Public
Document Table of Contents
Document Table of Contents x
1. GTS SDI II IP Quick Reference 2. GTS SDI II IP Core Overview 3. GTS SDI II IP Core Getting Started 4. GTS SDI II IP Parameters 5. GTS SDI II IP Core Functional Description 6. GTS SDI II IP Core Signals 7. GTS SDI II IP Core Design Considerations 8. GTS SDI II IP Core Testbench and Design Examples 9. Document Revision History for the GTS SDI II IP User Guide
2. GTS SDI II IP Core Overview x
2.1. Release Information 2.2. Device Family Support 2.3. General Description 2.4. Performance and Resource Utilization
3. GTS SDI II IP Core Getting Started x
3.1. Installing and Licensing IP Cores 3.2. Design Walkthrough 3.3. GTS SDI II IP Core Component Files 3.4. Compiling the GTS SDI II IP Core Design 3.5. Programming an FPGA
3.1. Installing and Licensing IP Cores x
3.1.1. Intel FPGA IP Evaluation Mode
3.2. Design Walkthrough x
3.2.1. Creating a New Quartus® Prime Project 3.2.2. Launching IP Catalog 3.2.3. Parameterizing the IP Core 3.2.4. Generating a Design Example and Simulation Testbench
5. GTS SDI II IP Core Functional Description x
5.1. Protocol 5.2. Transceiver 5.3. Submodules 5.4. Optional Features
5.1. Protocol x
5.1.1. Transmitter 5.1.2. Receiver
5.3. Submodules x
5.3.1. Insert Line 5.3.2. Insert/Check CRC 5.3.3. Insert Payload ID 5.3.4. Match TRS 5.3.5. Scrambler 5.3.6. TX Sample 5.3.7. Clock Enable Generator 5.3.8. RX Sample 5.3.9. Detect Video Standard 5.3.10. Detect 1 and 1/1.001 Rates 5.3.11. Transceiver Controller 5.3.12. Descrambler 5.3.13. TRS Aligner 5.3.14. 3Gb Demux 5.3.15. Extract Line 5.3.16. Extract Payload ID 5.3.17. Detect Format 5.3.18. Sync Streams 5.3.19. Convert SD Bits 5.3.20. Insert Sync Bits 5.3.21. Remove Sync Bits
5.4. Optional Features x
5.4.1. SMPTE RP168 Switching Support 5.4.2. SD 20-Bit Interface for Dual/Triple Rate 5.4.3. Intel FPGA Video Streaming Interface
5.4.3. Intel FPGA Video Streaming Interface x
5.4.3.1. RGB Pixel Packing 5.4.3.2. YCbCr 444 Pixel Packing 5.4.3.3. YCbCr 422 Pixel Packing 5.4.3.4. Supported Modes
6. GTS SDI II IP Core Signals x
6.1. GTS SDI II IP Core Resets and Clocks 6.2. Transmitter Protocol Signals 6.3. Receiver Protocol Signals 6.4. Transceiver Signals 6.5. Transmitter Streaming Video and Control Signals 6.6. Receiver Streaming Video and Control Signals
6.2. Transmitter Protocol Signals x
6.2.1. Image Mapping
6.3. Receiver Protocol Signals x
6.3.1. rx_format
7. GTS SDI II IP Core Design Considerations x
7.1. Transceiver Handling Guidelines 7.2. Dual Simplex Merging Tool (DS tool)
7.1. Transceiver Handling Guidelines x
7.1.1. Handling Transceiver in Agilex™ 5 Devices
7.1.1. Handling Transceiver in Agilex™ 5 Devices x
7.1.1.1. System PLL Clocking Mode 7.1.1.2. Unused Transceiver Tiles 7.1.1.3. SmartVID Settings
7.2. Dual Simplex Merging Tool (DS tool) x
7.2.1. Using the DS Tool
8. GTS SDI II IP Core Testbench and Design Examples x
8.1. Design Examples for Agilex™ 5 Devices
1. GTS SDI II IP Quick Reference
2. GTS SDI II IP Core Overview
3. GTS SDI II IP Core Getting Started
4. GTS SDI II IP Parameters
5. GTS SDI II IP Core Functional Description
6. GTS SDI II IP Core Signals
7. GTS SDI II IP Core Design Considerations
8. GTS SDI II IP Core Testbench and Design Examples
9. Document Revision History for the GTS SDI II IP User Guide

1. GTS SDI II IP Quick Reference

Updated for:
Intel® Quartus® Prime Design Suite 24.3
IP Version 1.0.0

The GTS Serial Digital Interface (SDI) II IP is the next generation SDI IP core. The GTS Serial Digital Interface (SDI) II IP will be referred to as GTS SDI II IP core for simplification purposes.

The GTS SDI II IP core is part of the IP Library, which is distributed with the Quartus® Prime software and downloadable from the Altera website.

Note: For system requirements and installation instructions, refer to the Altera FPGA Software Installation & Licensing manual.
Table 1.  Brief Information About the GTS SDI II IP Core
Information Description
IP Core Information SDI Data Rate Support
  • 1.485-Gbps or 1.4835-Gbps HD-SDI, as defined by SMPTE ST 292 specification
  • 2.97-Gbps or 2.967-Gbps 3G-SDI, as defined by SMPTE ST 424 specification
  • 11.88-Gbps or 11.868-Gbps 12G-SDI, as defined by SMPTE ST 2082 specification
Features
  • Automatic detection of SDI standards and video transport formats
  • Payload identification packet (ST 352) insertion and extraction
  • Cyclical redundancy check (CRC) encoding and decoding (except SD)
  • Line number (LN) insertion and extraction (except SD)
  • Framing and extraction of video timing signals
  • Dual link HD-SDI data stream synchronization (except SD)
  • 3G-SDI with data mapped by ST 425-x mapping
  • 6G-SDI with data mapped by ST 2081-x mapping 1
  • 12G-SDI with data mapped by ST 2082-x mapping
  • Optional Altera® FPGA video streaming interface
Applications
  • Digital video equipment
  • Mixing and recording equipment
Device Family Support Agilex™ 5
Design Tools
  • IP Catalog in the Quartus® Prime software for design creation and compilation
  • Questa* Intel® FPGA Edition, ModelSim SE* , Riviera-PRO* , VCS* MX, and Xcelium* Parallel simulator software for design simulation or synthesis using Quartus® Prime tool
Related Information
1 This feature is not supported in the current release.
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