GTS SDI II IP User Guide

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ID 823539
Date 6/30/2025
Public
Document Table of Contents
Document Table of Contents x
1. GTS SDI II IP Quick Reference 2. GTS SDI II IP Core Overview 3. GTS SDI II IP Core Getting Started 4. GTS SDI II IP Parameters 5. GTS SDI II IP Core Functional Description 6. GTS SDI II IP Core Signals 7. GTS SDI II IP Core Design Considerations 8. GTS SDI II IP Core Testbench and Design Examples 9. Document Revision History for the GTS SDI II IP User Guide
2. GTS SDI II IP Core Overview x
2.1. Release Information 2.2. Device Family Support 2.3. General Description 2.4. Performance and Resource Utilization
3. GTS SDI II IP Core Getting Started x
3.1. Installing and Licensing IP Cores 3.2. Design Walkthrough 3.3. GTS SDI II IP Core Component Files 3.4. Compiling the GTS SDI II IP Core Design 3.5. Programming an FPGA
3.1. Installing and Licensing IP Cores x
3.1.1. Intel FPGA IP Evaluation Mode
3.2. Design Walkthrough x
3.2.1. Creating a New Quartus® Prime Project 3.2.2. Launching IP Catalog 3.2.3. Parameterizing the IP Core 3.2.4. Generating a Design Example and Simulation Testbench
5. GTS SDI II IP Core Functional Description x
5.1. Protocol 5.2. Transceiver 5.3. Submodules 5.4. Optional Features
5.1. Protocol x
5.1.1. Transmitter 5.1.2. Receiver
5.3. Submodules x
5.3.1. Insert Line 5.3.2. Insert/Check CRC 5.3.3. Insert Payload ID 5.3.4. Match TRS 5.3.5. Scrambler 5.3.6. TX Sample 5.3.7. Clock Enable Generator 5.3.8. RX Sample 5.3.9. Detect Video Standard 5.3.10. Detect 1 and 1/1.001 Rates 5.3.11. Transceiver Controller 5.3.12. Descrambler 5.3.13. TRS Aligner 5.3.14. 3Gb Demux 5.3.15. Extract Line 5.3.16. Extract Payload ID 5.3.17. Detect Format 5.3.18. Sync Streams 5.3.19. Convert SD Bits 5.3.20. Insert Sync Bits 5.3.21. Remove Sync Bits
5.4. Optional Features x
5.4.1. SMPTE RP168 Switching Support 5.4.2. SD 20-Bit Interface for Dual/Triple Rate 5.4.3. Intel FPGA Video Streaming Interface
5.4.3. Intel FPGA Video Streaming Interface x
5.4.3.1. RGB Pixel Packing 5.4.3.2. YCbCr 444 Pixel Packing 5.4.3.3. YCbCr 422 Pixel Packing 5.4.3.4. Supported Modes
6. GTS SDI II IP Core Signals x
6.1. GTS SDI II IP Core Resets and Clocks 6.2. Transmitter Protocol Signals 6.3. Receiver Protocol Signals 6.4. Transceiver Signals 6.5. Transmitter Streaming Video and Control Signals 6.6. Receiver Streaming Video and Control Signals
6.2. Transmitter Protocol Signals x
6.2.1. Image Mapping
6.3. Receiver Protocol Signals x
6.3.1. rx_format
7. GTS SDI II IP Core Design Considerations x
7.1. Transceiver Handling Guidelines 7.2. Dual Simplex Merging Tool (DS tool)
7.1. Transceiver Handling Guidelines x
7.1.1. Handling Transceiver in Agilex™ 5 Devices
7.1.1. Handling Transceiver in Agilex™ 5 Devices x
7.1.1.1. System PLL Clocking Mode 7.1.1.2. Unused Transceiver Tiles 7.1.1.3. SmartVID Settings
7.2. Dual Simplex Merging Tool (DS tool) x
7.2.1. Using the DS Tool
8. GTS SDI II IP Core Testbench and Design Examples x
8.1. Design Examples for Agilex™ 5 Devices
1. GTS SDI II IP Quick Reference
2. GTS SDI II IP Core Overview
3. GTS SDI II IP Core Getting Started
4. GTS SDI II IP Parameters
5. GTS SDI II IP Core Functional Description
6. GTS SDI II IP Core Signals
7. GTS SDI II IP Core Design Considerations
8. GTS SDI II IP Core Testbench and Design Examples
9. Document Revision History for the GTS SDI II IP User Guide

6.1. GTS SDI II IP Core Resets and Clocks

Table 14.  Resets and Clock Signals
Signal Width Direction Description
tx_rst 1 Input

Reset signal for the transmitter. This signal is active high and level sensitive.

This signal must be synchronous to tx_pclk clock domain.

rx_rst 1 Input

Reset signal for the receiver. This signal is active high and level sensitive. This reset signal must be synchronous to the rx_coreclk or rx_coreclk_hd clock domain.

rst_trig_rst 1 Output Reset output signal to the transceiver reset controller to reset the transceiver. This signal is synchronous to the rx_coreclk or rx_coreclk_hd clock domain.
tx_axi4s_reset 6 1 Input Tx AXI4-Stream reset.
rx_axi4s_reset 6 1 Input Rx AXI4-Stream reset.
tx_pclk 1 Input

Transmitter core parallel clock signal. This clock signal must be driven by the by parallel output clock from TX transceiver.

  • SD-SDI = 148.5 MHz
  • HD-SDI = 74.25 MHz or 74.175 MHz, depending on video frame rate
  • 3G-SDI = 148.5 MHz or 148.35 MHz, depending on video frame rate
  • HD-SDI Dual Link = 74.25 MHz or 74.175 MHz, depending on video frame rate
  • Dual Rate = 148.5 MHz or 148.35 MHz, depending on video frame rate
  • Triple Rate = 148.5 MHz or 148.35 MHz, depending on video frame rate
  • Multi Rate (up to 12G-SDI) = 148.5 MHz or 148.35 MHz, depending on video frame rate
rx_coreclk 1 Input
Receiver core clock signal. You can set the following frequencies:
  • 148.5-MHz or 148.35-MHz: Applicable for all configurations.
Note: For the Agilex™ 5 device, set the clock frequency range between 100 MHz to 156.25 MHz. Intel recommends sharing the same clock as the i_csr_clk port from the F-Tile Dynamic Reconfiguration Suite IP core.

This clock source must be stable and there are no required relationships with any other clocks. The clock source can be asynchronous or synchronous to any transceiver's clock.

Note: Not applicable if the selected transceiver reference clock frequency is 74.25 MHz/74.175 MHz.
xcvr_rxclk 1 Input

Receiver parallel clock input. Driven by rx_pma_div_clkout (for multi-rate modes) or rx_clkout (for other modes) from the transceiver.

  • SD-SDI = 148.5 MHz
  • HD-SDI = 74.25 MHz or 74.175 MHz, depending on video frame rate
  • 3G-SDI = 148.5 MHz or 148.35 MHz, depending on video frame rate
  • 6G-SDI = 148.5 MHz or 148.35 MHz, depending on video frame rate
  • 12G-SDI = 148.5 MHz or 148.35 MHz, depending on video frame rate
tx_axi4s_clk 6 1 Input TX AXI4-Stream clock.
rx_axi4s_clk 6 1 Input RX AXI4-Stream clock.
Figure 30. TX Clocking Diagram for Agilex™ 5 Devices


Figure 31. RX Clocking Diagram for Agilex™ 5 Devices


Note: For a more comprehensive TX and RX Agilex™ 5 clocking diagrams with transceivers, refer to the respective design example user guides.
6 Only available when Enable active video data protocols = AXIS-VVP Full.
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