GTS SDI II IP User Guide

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ID 823539
Date 9/30/2025
Public
Document Table of Contents
Document Table of Contents x
1. GTS SDI II IP Quick Reference 2. GTS SDI II IP Overview 3. GTS SDI II IP Core Getting Started 4. GTS SDI II IP Parameters 5. GTS SDI II IP Core Functional Description 6. GTS SDI II IP Core Signals 7. GTS SDI II IP Core Design Considerations 8. GTS SDI II IP Core Testbench and Design Examples 9. Document Revision History for the GTS SDI II IP User Guide
2. GTS SDI II IP Overview x
2.1. GTS SDI II Release Information 2.2. GTS SDI II IP Device Family Support 2.3. GTS SDI II IP General Description 2.4. Performance and Resource Utilization
3. GTS SDI II IP Core Getting Started x
3.1. Installing and Licensing IPs 3.2. Design Walkthrough 3.3. GTS SDI II IP Core Component Files 3.4. Compiling the GTS SDI II IP Core Design 3.5. Programming an FPGA
3.1. Installing and Licensing IPs x
3.1.1. IP Evaluation Mode
3.2. Design Walkthrough x
3.2.1. Creating a New Quartus® Prime Project 3.2.2. Launching IP Catalog 3.2.3. Parameterizing the IP Core 3.2.4. Generating a Design Example and Simulation Testbench
5. GTS SDI II IP Core Functional Description x
5.1. Protocol 5.2. Transceiver 5.3. Submodules 5.4. Optional Features
5.1. Protocol x
5.1.1. Transmitter 5.1.2. Receiver
5.3. Submodules x
5.3.1. Insert Line 5.3.2. Insert/Check CRC 5.3.3. Insert Payload ID 5.3.4. Match TRS 5.3.5. Scrambler 5.3.6. TX Sample 5.3.7. Clock Enable Generator 5.3.8. RX Sample 5.3.9. Detect Video Standard 5.3.10. Detect 1 and 1/1.001 Rates 5.3.11. Transceiver Controller 5.3.12. Descrambler 5.3.13. TRS Aligner 5.3.14. 3Gb Demux 5.3.15. Extract Line 5.3.16. Extract Payload ID 5.3.17. Detect Format 5.3.18. Sync Streams 5.3.19. Convert SD Bits 5.3.20. Insert Sync Bits 5.3.21. Remove Sync Bits
5.4. Optional Features x
5.4.1. SMPTE RP168 Switching Support 5.4.2. SD 20-Bit Interface for Dual/Triple Rate 5.4.3. Intel FPGA Video Streaming Interface
5.4.3. Intel FPGA Video Streaming Interface x
5.4.3.1. RGB Pixel Packing 5.4.3.2. YCbCr 444 Pixel Packing 5.4.3.3. YCbCr 422 Pixel Packing 5.4.3.4. Supported Modes
6. GTS SDI II IP Core Signals x
6.1. GTS SDI II IP Core Resets and Clocks 6.2. Transmitter Protocol Signals 6.3. Receiver Protocol Signals 6.4. Transceiver Signals 6.5. Transmitter Streaming Video and Control Signals 6.6. Receiver Streaming Video and Control Signals
6.2. Transmitter Protocol Signals x
6.2.1. Image Mapping
6.3. Receiver Protocol Signals x
6.3.1. rx_format
7. GTS SDI II IP Core Design Considerations x
7.1. Transceiver Handling Guidelines 7.2. Dual Simplex Merging Tool (DS tool)
7.1. Transceiver Handling Guidelines x
7.1.1. Handling Transceiver in Agilex™ 3 and Agilex™ 5 Devices
7.1.1. Handling Transceiver in Agilex™ 3 and Agilex™ 5 Devices x
7.1.1.1. System PLL Clocking Mode 7.1.1.2. Unused Transceiver Tiles 7.1.1.3. SmartVID Settings
7.2. Dual Simplex Merging Tool (DS tool) x
7.2.1. Using the DS Tool
8. GTS SDI II IP Core Testbench and Design Examples x
8.1. Design Examples for Agilex™ 5 Devices
1. GTS SDI II IP Quick Reference
2. GTS SDI II IP Overview
3. GTS SDI II IP Core Getting Started
4. GTS SDI II IP Parameters
5. GTS SDI II IP Core Functional Description
6. GTS SDI II IP Core Signals
7. GTS SDI II IP Core Design Considerations
8. GTS SDI II IP Core Testbench and Design Examples
9. Document Revision History for the GTS SDI II IP User Guide

5.4.3.2. YCbCr 444 Pixel Packing

The Altera FPGA Streaming Video Protocol specifies a packing scheme for YCbCr 444 pixels.

YCbCr pixels are always packed with Cb as the least significant symbol, then the Y symbol and then the Cr symbol. The following figure illustrates the 12 bits YCbCr 444 video packet transported over AXI4-Stream Video interface configured at Bits per color sample parameter set to 12 bits. In this example, each pixel (36 bits) does not perfectly fill a given number of bytes, hence additional 4 undefined bits are padded at the most significant bits of each pixel.

Figure 24. 12 Bits YCbCr 444 Video Packet When Parameter Bits Per Color Sample = 12

The following figure illustrates the 10 bits YCbCr 444 video packet transported over AXI4-Stream Video interface configured at IP parameter Bits per color sample parameter set to 12 bits. The active bits per color sample is less than the compile time parameter, hence the 2 least significant bits for each color sample are padded with zero.

Figure 25. 10 Bits YCbCr 444 Video Packet When Parameter Bits Per Color Sample = 12

The following figure illustrates the 10 bits YCbCr 444 video packet transported over AXI4-Stream Video interface configured at IP parameter Bits per color sample parameter set to 10 bits. Each pixel (30 bits) does not perfectly fill a given number of bytes, hence additional 2 undefined bits are padded at the most significant bits of each pixel.

Figure 26. 10 Bits YCbCr 444 Video Packet When Parameter Bits Per Color Sample = 10
Level Two Title