1. GTS SDI II IP Quick Reference
2. GTS SDI II IP Overview
3. GTS SDI II IP Core Getting Started
4. GTS SDI II IP Parameters
5. GTS SDI II IP Core Functional Description
6. GTS SDI II IP Core Signals
7. GTS SDI II IP Core Design Considerations
8. GTS SDI II IP Core Testbench and Design Examples
9. Document Revision History for the GTS SDI II IP User Guide
5.3.1. Insert Line
5.3.2. Insert/Check CRC
5.3.3. Insert Payload ID
5.3.4. Match TRS
5.3.5. Scrambler
5.3.6. TX Sample
5.3.7. Clock Enable Generator
5.3.8. RX Sample
5.3.9. Detect Video Standard
5.3.10. Detect 1 and 1/1.001 Rates
5.3.11. Transceiver Controller
5.3.12. Descrambler
5.3.13. TRS Aligner
5.3.14. 3Gb Demux
5.3.15. Extract Line
5.3.16. Extract Payload ID
5.3.17. Detect Format
5.3.18. Sync Streams
5.3.19. Convert SD Bits
5.3.20. Insert Sync Bits
5.3.21. Remove Sync Bits
2.2. GTS SDI II IP Device Family Support
Device Family | Support Level |
---|---|
Agilex™ 3 | Preliminary |
Agilex™ 5 | Preliminary |
The following terms define device support levels for IPs:
- Advance support—the IP is available for simulation and compilation for this device family. Timing models include initial engineering estimates of delays based on early post-layout information. The timing models are subject to change as silicon testing improves the correlation between the actual silicon and the timing models. You can use this IP for system architecture and resource utilization studies, simulation, pinout, system latency assessments, basic timing assessments (pipeline budgeting), and I/O transfer strategy (data-path width, burst depth, I/O standards tradeoffs).
- Preliminary support—the IP is verified with preliminary timing models for this device family. The IP meets all functional requirements, but might still be undergoing timing analysis for the device family. It can be used in production designs with caution.
- Final support—the IP is verified with final timing models for this device family. The IP meets all functional and timing requirements for the device family and can be used in production designs.