3.1.1. HDMI RX-TX Retransmit With Integrated Transceiver Design Parameters
3.1.2. Integrated Transceiver With Dual Simplex Block Diagram
3.1.3. Integrated Transceiver Without Dual Simplex Block Diagram
3.1.4. Agilex™ 5 HDMI RX-TX Retransmit With Integrated Transceiver Design Example Top Level Common Blocks
3.1.5. Agilex™ 5 HDMI RX-TX Retransmit With Integrated Transceiver Design Example Interface Signals
3.1.6. Agilex™ 5 HDMI RX-TX Retransmit With Integrated Transceiver Design Software Flow
3.1.7. Agilex™ 5 HDMI RX-TX Retransmit With Integrated Transceiver Design Hardware Setup
3.2.1. HDMI RX-TX Retransmit Without Integrated Transceiver Design Parameters
3.2.2. Non-Integrated Transceiver With Dual Simplex Block Diagram
3.2.3. Non-Integrated Transceiver Without Dual Simplex block diagram
3.2.4. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Example Top Level Common Blocks
3.2.5. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Example Interface Signals
3.2.6. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Software Flow
3.2.7. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Hardware setup
1. GTS HDMI IP Design Example Quick Start Guide for Agilex™ 5 Devices
Updated for: |
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Intel® Quartus® Prime Design Suite 25.1 |
IP Version 1.0.2 |
The GTS HDMI IP design example for Agilex™ 5 devices features a simulating testbench and a hardware design that supports compilation and hardware testing.
The GTS HDMI IP offers the following design examples:
- HDMI 2.0 Receiver-Transmitter (RX-TX) retransmit design with Transition Minimized Differential Signaling (TMDS) mode on clocked video interface enabled (without Integrated Transceiver).
- HDMI 2.0 Receiver-Transmitter (RX-TX) retransmit design with Transition Minimized Differential Signaling (TMDS) mode on clocked video interface enabled with Integrated Transceiver.
When you generate a design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.
Figure 1. Development Stages