GTS HDMI Intel® FPGA IP Design Example User Guide

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ID 823528
Date 5/15/2025
Public
Document Table of Contents
Document Table of Contents x
1. GTS HDMI IP Design Example Quick Start Guide for Agilex™ 5 Devices 2. Dual Simplex Mode with the HDMI Simplex IP 3. Design Example Variants 4. Simulation Testbench 5. Document Revision History for the GTS HDMI IP Design Example User Guide for Agilex™ 5 Devices
1. GTS HDMI IP Design Example Quick Start Guide for Agilex™ 5 Devices x
1.1. Design Description 1.2. Supported HDMI Features 1.3. Hardware and Software Requirements 1.4. Generating the Design 1.5. Simulating the Design 1.6. Compiling and Testing the Design
2. Dual Simplex Mode with the HDMI Simplex IP x
2.1. HDMI RX with Integrated Transceiver 2.2. HDMI TX with Integrated Transceiver 2.3. Requirement for Dual Simplex 2.4. Creating Dual Simplex Groups
2.1. HDMI RX with Integrated Transceiver x
2.1.1. HDMI RX Parameters for Integrated Transceiver
2.2. HDMI TX with Integrated Transceiver x
2.2.1. HDMI TX Parameters for Integrated Transceiver
3. Design Example Variants x
3.1. Agilex™ 5 HDMI RX-TX Retransmit with Integrated Transceiver Design Example Variant 3.2. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Example Variant
3.1. Agilex™ 5 HDMI RX-TX Retransmit with Integrated Transceiver Design Example Variant x
3.1.1. HDMI RX-TX Retransmit With Integrated Transceiver Design Parameters 3.1.2. Integrated Transceiver With Dual Simplex Block Diagram 3.1.3. Integrated Transceiver Without Dual Simplex Block Diagram 3.1.4. Agilex™ 5 HDMI RX-TX Retransmit With Integrated Transceiver Design Example Top Level Common Blocks 3.1.5. Agilex™ 5 HDMI RX-TX Retransmit With Integrated Transceiver Design Example Interface Signals 3.1.6. Agilex™ 5 HDMI RX-TX Retransmit With Integrated Transceiver Design Software Flow 3.1.7. Agilex™ 5 HDMI RX-TX Retransmit With Integrated Transceiver Design Hardware Setup
3.2. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Example Variant x
3.2.1. HDMI RX-TX Retransmit Without Integrated Transceiver Design Parameters 3.2.2. Non-Integrated Transceiver With Dual Simplex Block Diagram 3.2.3. Non-Integrated Transceiver Without Dual Simplex block diagram 3.2.4. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Example Top Level Common Blocks 3.2.5. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Example Interface Signals 3.2.6. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Software Flow 3.2.7. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Hardware setup
4. Simulation Testbench x
4.1. Non-Integrated Transceiver Simulation Testbench 4.2. Integrated Transceiver (With Dual Simplex) Simulation Testbench 4.3. Simulation Testbench Parameters 4.4. Simulation Time Benchmark
1. GTS HDMI IP Design Example Quick Start Guide for Agilex™ 5 Devices
2. Dual Simplex Mode with the HDMI Simplex IP
3. Design Example Variants
4. Simulation Testbench
5. Document Revision History for the GTS HDMI IP Design Example User Guide for Agilex™ 5 Devices

3.1.7. Agilex™ 5 HDMI RX-TX Retransmit With Integrated Transceiver Design Hardware Setup

To run the hardware test, connect an HDMI-enabled device—such as a graphics card with HDMI interface—to the HDMI sink input. The design supports HDMI 2.0/1.4b source and sink.
  1. The HDMI sink decodes the port into a standard video stream and sends it to the clock recovery core.
  2. The HDMI RX core decodes the video, auxiliary, and audio data to be looped back in parallel to the HDMI TX IP through the DCFIFO.
  3. The HDMI source port of the FMC daughter card transmits the image to a monitor.

If you want to use another FPGA development board, you must change the device assignments and the pin assignments. Altera tests the transceiver analog setting for the Agilex 5 FPGA development kit and Bitec HDMI 2.1 daughtercard. You may modify the settings for your own board.

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