GTS HDMI Intel® FPGA IP Design Example User Guide

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ID 823528
Date 5/15/2025
Public
Document Table of Contents
Document Table of Contents x
1. GTS HDMI IP Design Example Quick Start Guide for Agilex™ 5 Devices 2. Dual Simplex Mode with the HDMI Simplex IP 3. Design Example Variants 4. Simulation Testbench 5. Document Revision History for the GTS HDMI IP Design Example User Guide for Agilex™ 5 Devices
1. GTS HDMI IP Design Example Quick Start Guide for Agilex™ 5 Devices x
1.1. Design Description 1.2. Supported HDMI Features 1.3. Hardware and Software Requirements 1.4. Generating the Design 1.5. Simulating the Design 1.6. Compiling and Testing the Design
2. Dual Simplex Mode with the HDMI Simplex IP x
2.1. HDMI RX with Integrated Transceiver 2.2. HDMI TX with Integrated Transceiver 2.3. Requirement for Dual Simplex 2.4. Creating Dual Simplex Groups
2.1. HDMI RX with Integrated Transceiver x
2.1.1. HDMI RX Parameters for Integrated Transceiver
2.2. HDMI TX with Integrated Transceiver x
2.2.1. HDMI TX Parameters for Integrated Transceiver
3. Design Example Variants x
3.1. Agilex™ 5 HDMI RX-TX Retransmit with Integrated Transceiver Design Example Variant 3.2. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Example Variant
3.1. Agilex™ 5 HDMI RX-TX Retransmit with Integrated Transceiver Design Example Variant x
3.1.1. HDMI RX-TX Retransmit With Integrated Transceiver Design Parameters 3.1.2. Integrated Transceiver With Dual Simplex Block Diagram 3.1.3. Integrated Transceiver Without Dual Simplex Block Diagram 3.1.4. Agilex™ 5 HDMI RX-TX Retransmit With Integrated Transceiver Design Example Top Level Common Blocks 3.1.5. Agilex™ 5 HDMI RX-TX Retransmit With Integrated Transceiver Design Example Interface Signals 3.1.6. Agilex™ 5 HDMI RX-TX Retransmit With Integrated Transceiver Design Software Flow 3.1.7. Agilex™ 5 HDMI RX-TX Retransmit With Integrated Transceiver Design Hardware Setup
3.2. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Example Variant x
3.2.1. HDMI RX-TX Retransmit Without Integrated Transceiver Design Parameters 3.2.2. Non-Integrated Transceiver With Dual Simplex Block Diagram 3.2.3. Non-Integrated Transceiver Without Dual Simplex block diagram 3.2.4. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Example Top Level Common Blocks 3.2.5. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Example Interface Signals 3.2.6. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Software Flow 3.2.7. Agilex™ 5 HDMI RX-TX Retransmit Without Integrated Transceiver Design Hardware setup
4. Simulation Testbench x
4.1. Non-Integrated Transceiver Simulation Testbench 4.2. Integrated Transceiver (With Dual Simplex) Simulation Testbench 4.3. Simulation Testbench Parameters 4.4. Simulation Time Benchmark
1. GTS HDMI IP Design Example Quick Start Guide for Agilex™ 5 Devices
2. Dual Simplex Mode with the HDMI Simplex IP
3. Design Example Variants
4. Simulation Testbench
5. Document Revision History for the GTS HDMI IP Design Example User Guide for Agilex™ 5 Devices

1.3. Hardware and Software Requirements

Use the following hardware and software to test the GTS HDMI IP design example.
Hardware:
  • Agilex 5 FPGA E-Series 065B Premium Development Kit
  • Bitec* HDMI FMC 2.1 daughter card (Revision 9)
  • HDMI 2.0 Source

    This design example was developed and tested using a Quantum Data* 980 18G Generator. Use this HDMI source or an equivalent.

  • HDMI 2.0 Sink

    This design example was developed and tested using a Quantum Data* 980 18G Analyzer. Use this HDMI sink or an equivalent.

  • HDMI 2.1 Category 3 cables

    This design example was developed and tested using a Belkin* 48 Gbps HDMI 2.1 cable. Use this cable or an equivalent.

Software:

  • Quartus® Prime Pro Edition
  • One of the following simulation software packages:
    • Questa* Intel® FPGA Edition
    • Questa* Intel® FPGA Starter Edition
    • Synopsys* VCS* MX
    • Cadence* Xcelium* Parallel Logic Simulation
Level Two Title