GTS Interlaken IP Design Example User Guide

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ID 819203
Date 3/30/2025
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1.2. Generating the GTS Interlaken Design Example

Figure 3. Procedure
Follow these steps to generate the design example and testbench:
  1. In the Quartus® Prime Pro Edition software, click File > New Project Wizard to create a new Quartus® Prime project, or click File > Open Project to open an existing Quartus® Prime project. The wizard prompts you to specify a device.
  2. Specify the device family Agilex™ 5 (D-Series/E-Series) and select device with GTS for your design.
  3. In the IP Catalog, locate and double-click GTS Interlaken Intel FPGA IP. The New IP Variant window appears.
  4. Specify a top-level name <your_ip> for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.ip.
  5. Click OK. The parameter editor appears.
    Figure 4. Example Design Tab
  6. On the IP tab, specify the parameters for your IP core variation.
  7. On the Example Design tab, select the Simulation option to generate the testbench. Select the Synthesis option to generate the hardware design example. You must select at least one of the Simulation and Synthesis options to generate the design example.
  8. For Generated HDL Format, both Verilog and VHDL option is available.
  9. Under Target Development Kit for Select Board, select Agilex 5 FPGA E-Series 065B Premium Development Kit (ES1).
    The software sets the pin assignments for that development kit and device part number. To test the design on hardware on a different PCB, select None and make the appropriate pin assignments in the .qsf file.
  10. Click Generate Example Design. The Select Example Design Directory window appears.
  11. If you want to modify the design example directory path or name from the defaults displayed (intel_ilk_gts_0_example_design), browse to the new path and type the new design example directory name.
  12. Click OK.
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