1.3. Directory Structure

GTS Interlaken IP Design Example User Guide

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ID 819203

Date 3/30/2025

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Public

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The GTS Interlaken Altera® FPGA IP generates the following files for the design example:

Figure 5. Directory Structure

Note: ila is not supported for GTS platform in Quartus® Prime version 25.1.

Table 2. Hardware Design Example File DescriptionsThese files are in the <`design_example_installation_dir`>/ilk_gts_0_example_design directory.
File Names	Description
example_design.qpf	Quartus® Prime project file.
example_design.qsf	Quartus® Prime project settings file
example_design.sdc jtag_timing_template.sdc	Synopsys* Design Constraint file. You can copy and modify for your own design.

Table 3. Testbench File DescriptionThis file is in the <`design_example_installation_dir`>/ilk_gts_0_example_design/example_design/rtl directory.
File Name	Description
top_tb.sv	Top-level testbench file.

Table 4. Testbench ScriptsThese files are in the <`design_example_installation_dir`>/ilk_gts_0_example_design/example_design/testbench directory.
File Name	Description
run_vcsmx.sh	The Synopsys* VCS* MX script to run the testbench.
run_mentor.tcl	The Siemens* EDA QuestaSim* script to run the testbench.
run_xcelium.sh	The Cadence* Xcelium* script to run the testbench.
run_riviera.tcl	The Riviera-PRO script to run the testbench.