GTS Interlaken Intel® FPGA IP User Guide

ID 819200
Date 1/13/2025
Public
Document Table of Contents

1.4. GTS Interlaken IP Performance and Resources

The tables show resources and expected performance for selected variations of the Interlaken IP using the Quartus® Prime Pro Edition software. Your results may slightly vary depending on the device you select.

For a list of supported configurations, refer to IP Supported Combinations of Number of Lanes and Data Rates

Table 4.  Resource Utilization for Interleaved Mode (Number of Segments = 1)
Transceiver Mode PMA Type Data Rate (Gbps) Number of Lanes ALM Logic Register (Primary) Logic Register (Secondary) M20K
NRZ FGT 6.25 4 22,492.7 40,152 7,366 32
12.5 4 22,441.9 40,285 7,498 32
8 46,348.8 80,531 13,920 60
Table 5.  Resource Utilization for Multisegment (Packet)
Transceiver Mode PMA Type Data Rate (Gbps) Number of Lanes ALM Logic Register (Primary) Logic Register (Secondary) M20K
NRZ FGT 6.25 4 22,472.9 40,155 7,471 32
12.5 4 22,417.9 40,293 7,429 32
8 46,430.6 80,209 14,141 60