External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs
- 4.1.2. s0_axi4_clock_out for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component
- 4.2.2. s0_axi4_clock_out for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component
5.1. Simulation Walkthrough
A given design may display different latency values on different boards, due to differences in board implementation.
The Agilex™ 5 EMIF IP supports functional simulation through the design example using the traffic generator IP.
To perform functional simulation for an Agilex™ 5 EMIF IP design example, locate the design example files in the design example directory.
You can use the IP functional simulation model with any supported VHDL or Verilog HDL simulator.
After you have generated the memory IP, you can locate multiple file sets for various supported simulations in the sim/ed_sim subdirectory. For more information about the EMIF simulation design example, refer to the External Memory Interfaces Agilex™ 5 FPGA IP Design Example User Guide.