External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs
ID
817467
Date
7/07/2025
Public
1. About the External Memory Interfaces Agilex™ 5 FPGA IP
2. Agilex™ 5 FPGA EMIF IP – Introduction
3. Agilex™ 5 FPGA EMIF IP – Product Architecture
4. Agilex™ 5 FPGA EMIF IP – End-User Signals
5. Agilex™ 5 FPGA EMIF IP – Simulating Memory IP
6. Agilex™ 5 FPGA EMIF IP - DDR4 Support
7. Agilex™ 5 FPGA EMIF IP - DDR5 Support
8. Agilex™ 5 FPGA EMIF IP - LPDDR4 Support
9. Agilex™ 5 FPGA EMIF IP - LPDDR5 Support
10. Agilex™ 5 FPGA EMIF IP – Timing Closure
11. Agilex™ 5 FPGA EMIF IP – Controller Optimization
12. Agilex™ 5 FPGA EMIF IP – Debugging
13. Agilex™ 5 FPGA EMIF IP - Mailbox Support
14. Document Revision History for External Memory Interfaces (EMIF) IP User Guide
3.1. Agilex™ 5 EMIF Architecture: Protocol and Maximum Interface Width Support
3.2. Agilex™ 5 EMIF Architecture: Protocol and Maximum Supported Capacity
3.3. Agilex™ 5 EMIF Architecture: Introduction
3.4. Agilex™ 5 EMIF Sequencer
3.5. Agilex™ 5 EMIF Calibration Time
3.6. Agilex™ 5 EMIF Controller
3.7. Agilex™ 5 EMIF IP for Hard Processor Subsystem (HPS)
3.3.1. Agilex™ 5 EMIF Architecture: I/O Subsystem
3.3.2. Agilex™ 5 EMIF Architecture: I/O SSM
3.3.3. Agilex™ 5 EMIF Architecture: HSIO Bank
3.3.4. Agilex™ 5 EMIF Architecture: I/O Lane
3.3.5. Agilex™ 5 EMIF Architecture: Input DQS Clock Tree
3.3.6. Agilex™ 5 EMIF Architecture: PHY Clock Tree
3.3.7. Agilex™ 5 EMIF Architecture: PLL Reference Clock Networks
3.3.8. Agilex™ 5 EMIF Architecture: Clock Phase Alignment
3.3.9. User Clock in Different Core Access Modes
4.1. IP Interfaces for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component
4.2. IP Interfaces for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component
4.3. IP Interfaces for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4
4.4. IP Interfaces for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5
4.1.1. s0_axi4_clock_in for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component
4.1.2. s0_axi4_clock_out for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component
4.1.3. s0_axi4_ctrl_ready for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component
4.1.4. core_init_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component
4.1.5. s0_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component
4.1.6. s0_axi4lite_clock for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component
4.1.7. s0_axi4lite_reset_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component
4.1.8. s0_axi4lite for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component
4.1.9. mem_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component
4.1.10. mem_ck_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component
4.1.11. mem_reset_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component
4.1.12. oct_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component
4.1.13. ref_clk for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component
4.2.1. s0_axi4_clock_in for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component
4.2.2. s0_axi4_clock_out for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component
4.2.3. s0_axi4_ctrl_ready for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component
4.2.4. core_init_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component
4.2.5. s0_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component
4.2.6. s1_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component
4.2.7. s0_axi4lite_clock for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component
4.2.8. s0_axi4lite_reset_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component
4.2.9. s0_axi4lite for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component
4.2.10. mem_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component
4.2.11. mem_ck_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component
4.2.12. mem_reset_n_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component
4.2.13. mem_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component
4.2.14. mem_ck_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component
4.2.15. mem_reset_n_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component
4.2.16. oct_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component
4.2.17. oct_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component
4.2.18. ref_clk for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component
4.3.1. s0_axi4_clock_in for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4
4.3.2. core_init_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4
4.3.3. s0_axi4_ctrl_ready for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4
4.3.4. s0_axi4_clock_out for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4
4.3.5. s1_axi4_ctrl_ready for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4
4.3.6. s1_axi4_clock_out for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4
4.3.7. s0_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4
4.3.8. s1_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4
4.3.9. s2_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4
4.3.10. s3_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4
4.3.11. s0_axi4lite_clock for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4
4.3.12. s0_axi4lite_reset_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4
4.3.13. s0_axi4lite for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4
4.3.14. s1_axi4lite_clock for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4
4.3.15. s1_axi4lite_reset_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4
4.3.16. s1_axi4lite for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4
4.3.17. mem_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4
4.3.18. mem_ck_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4
4.3.19. mem_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4
4.3.20. mem_ck_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4
4.3.21. mem_2 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4
4.3.22. mem_ck_2 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4
4.3.23. mem_3 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4
4.3.24. mem_ck_3 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4
4.3.25. mem_reset_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4
4.3.26. oct_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4
4.3.27. oct_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4
4.3.28. oct_2 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4
4.3.29. oct_3 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4
4.3.30. ref_clk for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR4
4.4.1. s0_axi4_clock_in for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5
4.4.2. core_init_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5
4.4.3. s0_axi4_ctrl_ready for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5
4.4.4. s0_axi4_clock_out for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5
4.4.5. s1_axi4_ctrl_ready for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5
4.4.6. s1_axi4_clock_out for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5
4.4.7. s0_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5
4.4.8. s1_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5
4.4.9. s2_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5
4.4.10. s3_axi4 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5
4.4.11. s0_axi4lite_clock for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5
4.4.12. s0_axi4lite_reset_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5
4.4.13. s0_axi4lite for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5
4.4.14. s1_axi4lite_clock for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5
4.4.15. s1_axi4lite_reset_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5
4.4.16. s1_axi4lite for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5
4.4.17. mem_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5
4.4.18. mem_ck_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5
4.4.19. mem_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5
4.4.20. mem_ck_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5
4.4.21. mem_2 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5
4.4.22. mem_ck_2 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5
4.4.23. mem_3 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5
4.4.24. mem_ck_3 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5
4.4.25. mem_reset_n for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5
4.4.26. oct_0 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5
4.4.27. oct_1 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5
4.4.28. oct_2 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5
4.4.29. oct_3 for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5
4.4.30. ref_clk for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - LPDDR5
6.3.3.1. Address and Command Pin Placement for DDR4
6.3.3.2. DDR4 Data Width Mapping
6.3.3.3. Clamshell Topology
6.3.3.4. General Guidelines - DDR4
6.3.3.5. x4 DIMM Implementation
6.3.3.6. Specific Pin Connection Requirements
6.3.3.7. Command and Address Signals
6.3.3.8. Clock Signals
6.3.3.9. Data, Data Strobes, DM/DBI, and Optional ECC Signals
12.1. Interface Configuration Performance Issues
12.2. Functional Issue Evaluation
12.3. Timing Issue Characteristics
12.4. Verifying Memory IP Using the Signal Tap Logic Analyzer
12.5. Debugging with the External Memory Interface Debug Toolkit
12.6. Generating Traffic with the Test Engine IP
12.7. Guidelines for Developing HDL for Traffic Generator
12.8. Guidelines for Traffic Generator Status Check
12.9. Hardware Debugging Guidelines
12.10. Categorizing Hardware Issues
12.9.1. Create a Simplified Design that Demonstrates the Same Issue
12.9.2. Measure Power Distribution Network
12.9.3. Measure Signal Integrity and Setup and Hold Margin
12.9.4. Vary Voltage
12.9.5. Operate at a Lower Speed
12.9.6. Determine Whether the Issue Exists in Previous Versions of Software
12.9.7. Determine Whether the Issue Exists in the Current Version of Software
12.9.8. Try A Different PCB
12.9.9. Try Other Configurations
12.9.10. Debugging Checklist
12.10.1.1. Characteristics of Signal Integrity Issues
12.10.1.2. Evaluating Signal Integrity Issues
12.10.1.3. Skew
12.10.1.4. Crosstalk
12.10.1.5. Power System
12.10.1.6. Clock Signals
12.10.1.7. Address and Command Signals
12.10.1.8. Read Data Valid Window and Eye Diagram
12.10.1.9. Write Data Valid Window and Eye Diagram
- 4.1.2. s0_axi4_clock_out for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR4 Component
- 4.2.2. s0_axi4_clock_out for Agilex 5 E-Series External Memory Interfaces (EMIF) IP - DDR5 Component
5.1.4. Simulating the Design Example
This topic describes how to simulate the design example in Synopsys* , and Siemens EDA simulators.
To run a simulation, navigate to the simulation directory <example_design_directory>/sim/ed_sim/ and run the simulation script of your choice.
For ModelSim* SE and Siemens* EDA QuestaSim*- Intel FPGA Edition Simulators
- At the command prompt, change the working directory to the following:
<example_design_directory>/sim/ed_sim/mentor
- Invoke vsim by typing:
vsim
The system launches a terminal window where you can run the commands described in the following steps. - Run the following command in the terminal window:
source msim_setup.tcl
- Run the following command in the terminal window:
ld_debug
- To select a signal to observe, right-click and select Add Wave from the context menu.
- To run the simulation, type:
run -all
Upon successful completion, the simulation displays the following message:
Simulation stopped due to successful completion!
For VCSMX Simulator
At the command prompt, change the working directory to the following: <example_design_directory>/sim/ed_sim/synopsys/vcsmx
Non-interactive Mode
To run a simulation in non-interactive mode, proceed as follows:
- Type the following command on a single line:
sh vcsmx_setup.sh USER_DEFINED_COMPILE_OPTIONS="" USER_DEFINED_ELAB_OPTIONS="-xlrm\ uniq_prior_final" USER_DEFINED_SIM_OPTIONS=""
The system performs the simulation and displays the following message upon successful completion:
Simulation stopped due to successful completion!
Interactive Mode
To run a simulation in interactive mode, proceed as described below.
Note: If you have already generated a simv executable in non-interactive mode, delete the simv and simv.diadir files within the vcsmx folder.
- Open the vcs_setup.sh file in an editor and add a -debug_access+r command, as highlighted in the figure below:
- Compile the design example by typing:
sh vcs_setup.sh USER_DEFINED_ELAB_OPTIONS="-xlrm\ uniq_prior_final" SKIP_SIM=1
- To start the simulation in interactive mode, type the following command in the terminal console:
simv -gui&