External Memory Interfaces (EMIF) IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 817467
Date 11/18/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.4.3. s0_axi4_clock_in for External Memory Interfaces (EMIF) IP - DDR5 DIMM

Input user clock for mainband; for MAINBAND_ACCESS_MODE = ASYNC only.

Table 64.  Interface: s0_axi4_clock_inInterface type: clock
Port Name Direction Description
s0_axi4_clock_in Input User clock for mainband axi. Input clock to the EMIF IP, no relationship to PHY clock.