External Memory Interfaces (EMIF) IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 817394
Date 7/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 5 FPGA IP 2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP 3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP 4. Document Revision History for External Memory Interfaces (EMIF) IP Design Example User Guide
1. About the External Memory Interfaces Agilex™ 5 FPGA IP x
1.1. Release Information
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP x
2.1. Creating an EMIF Project 2.2. Generating and Configuring the EMIF IP 2.3. Configuring DQ Pin Swizzling 2.4. Generating the Synthesizable EMIF Design Example 2.5. Generating the EMIF Design Example for Simulation 2.6. Pin Placement for Agilex™ 5 EMIF IP 2.7. Compiling the Agilex™ 5 EMIF Design Example 2.8. Using the Design Example with the Test Engine IP 2.9. Generating the EMIF Design Example with the Performance Monitor
2.2. Generating and Configuring the EMIF IP x
2.2.1. Agilex™ 5 EMIF Parameter Editor Guidelines
2.3. Configuring DQ Pin Swizzling x
2.3.1. Example: DQ Pin Swizzling Within DQS Group for x32+ECC DDR4 Interface 2.3.2. Example: Byte Swizzling for x32 DDR4 Interface, Using a Memory Device of x8 Width 2.3.3. Combining Pin and Byte Swizzling 2.3.4. Example: Swizzling for x32 + ECC DDR4 Interface 2.3.5. Example: Swizzling for a 2-Channel x32 + ECC Interface 2.3.6. Example: Byte Swizzling for Lockstep Configuration
3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP x
3.1. Synthesis Design Example 3.2. Simulation Design Example 3.3. Example Design Tab
3.2. Simulation Design Example x
3.2.1. Running Simulation
1. About the External Memory Interfaces Agilex™ 5 FPGA IP
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 5 FPGA IP
3. Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP
4. Document Revision History for External Memory Interfaces (EMIF) IP Design Example User Guide

4. Document Revision History for External Memory Interfaces (EMIF) IP Design Example User Guide

Document Version Quartus® Prime Version IP Version Changes
2025.07.07 25.1.1  
  • In the Quick Start chapter:
    • Recast text in the Pin Assignments section of the Pin Placement for Agilex™ 5 EMIF IP topic.
    • Minor text addition in the Compiling the Agilex™ 5 EMIF Design Example topic.
    • Minor text addition in step 3 of the Generating the EMIF Design Example with the Performance Monitor topic.
2025.03.31 25.1 3.0.0
  • In the Quick Start chapter:
    • Modified the second table and the text in the Example: Swizzling for a 2-Channel x32 + ECC Interface topic.
    • Added examples to the Example: Byte Swizzling for Lockstep Configuration topic.
2025.01.13 24.3.1 2.0.0
  • In the Design Example Quick Start chapter, added the Example: Swizzling for a 2-Channel x32 + ECC Interface topic.
2024.11.18 24.3 1.0.0
  • in the About the External Memory Interfaces IP chapter, updated the table of IPs and associated version numbers.
  • In the Design Example Quick Start Guide for External Memory Interfaces chapter:
    • Updated several figures and screenshots throughout.
    • In the Agilex™ 5 EMIF Parameter Editor Guidelines topic, modified the table.
    • Removed Generating a Custom Memory Presets File and Using Custom Memory Device Presets from a File topics.
  • In the Design Example Description for External Memory Interfaces Agilex™ 5 FPGA IP chapter, modified the For Synopsys VCS-MX and Cadence Xcelium section of the Running Simulation topic.
2024.07.08 24.2 6.2.0
  • Reorganized some content of the Configuring DQ Pin Swizzling topic into several subtopics.
  • In the Quick Start chapter, modified step 7 in the Generating the EMIF Design Example with the Performance Monitor topic.
2024.04.01 24.1 6.1.0 Initial release.
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