Agilex™ 3 FPGAs and SoCs Device Overview

ID 817231
Date 4/22/2025
Public
Document Table of Contents

22. Revision History for the Agilex™ 3 FPGAs and SoCs Device Overview

Document Version Changes
2025.04.22
  • Updated mention of cryptography to Cryptographic Services.
  • Updated the note about the MIPI* D-PHY* interface in Table: Agilex™ 3 FPGAs and SoCs C-Series and Table: Agilex™ 3 FPGAs and SoCs Summary of Features.
  • Updated the number of general purpose I/Os available for Agilex™ 3 FPGAs and SoCs in Table: Agilex™ 3 FPGAs and SoCs Summary of Features.
  • Updated the HPS and PCIe* descriptions in Table: Agilex™ 3 FPGAs and SoCs Summary of Features.
  • Updated Table: C-Series FPGA Family Plan—Transceivers and HPS.
  • Updated Figure: Package Options, Migrations, and I/O Pins—C-Series:
    • Updated the number of VPBGA pins in the B23C package pin from 875 to 931.
    • Added the LVDS pair counts.
  • Updated Figure: Agilex™ 3 FPGAs and SoCs Ordering Part Number.
  • Updated Figure: Agilex™ 3 SoCs HPS Block Diagram.
  • Updated Table: Summary of Agilex™ 3 SoCs Key Features.
  • Updated the footnote for HSIO's MIPI* D-PHY* in Table: I/O Standards Support and Performance.
  • Updated the SEU Error Detection and Correction in Agilex™ 3 FPGAs and SoCs topic.
2024.09.23 Initial release.