2.1. Agilex™ 3 FPGAs and SoCs C-Series

Agilex™ 3 FPGAs and SoCs Device Overview

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ID 817231

Date 9/30/2025

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2.1. Agilex™ 3 FPGAs and SoCs C-Series

Table 4. C-Series FPGA Family Plan—Core FeaturesThe values in this table are maximum resources or performance.
Device	Logic Element	Adaptive Logic Module	M20K		MLAB		DSP
Device	Logic Element	Adaptive Logic Module	Count	Size (Mb)	Count	Size (Mb)	18×19 Multipliers	Peak INT8 (TOPS⁵ )
A3C 025	25,075	8,500	65	1.27	450	0.27	68	0.67
A3C 050	47,200	16,000	123	2.40	800	0.49	130	1.27
A3C 065	65,490	22,200	169	3.30	1,050	0.64	176	1.72
A3C 100	100,300	34,000	262	5.12	2,000	1.22	276	2.70
A3C 135	135,110	45,800	353	6.89	2,300	1.40	368	3.60

Table 5. C-Series FPGA Family Plan—I/Os and InterfacesThe values in this table are maximum resources or performance.
Device	HVIO (1.8 V–3.3 V)	HSIO (1.0 V–1.3 V)	PLL Count		1.3 V LVDS Pairs at 1.25 Gbps	LPDDR4 Interface (×32)	MIPI* D-PHY* Interface
Device	HVIO (1.8 V–3.3 V)	HSIO (1.0 V–1.3 V)	I/O PLL⁶	System PLL⁷	1.3 V LVDS Pairs at 1.25 Gbps	LPDDR4 Interface (×32)	MIPI* D-PHY* Interface
A3C 025	160	96	7	0	48	0	7
A3C 050	160	96	7	0	48	1	7
A3C 065	160	96	7	0	48	1	7
A3C 100	200	192	11	1	96	2	14
A3C 135	200	192	11	1	96	2	14

Table 6. C-Series FPGA Family Plan—Transceivers and HPS
The values in this table are maximum resources or performance.
Device	PCIe* 3.0 ×4	HPS
Device	PCIe* 3.0 ×4	Processor	Cache Size
A3C 025	—	—	—
A3C 050	—	—	—
A3C 065	—	—	—
A3C 100	1	Dual core Arm* Cortex* -A55 up to 800 MHz	Shared: 1 MB L3 Cortex* -A55: 32 KB L1 128 KB L2
A3C 135	1	Dual core Arm* Cortex* -A55 up to 800 MHz	Shared: 1 MB L3 Cortex* -A55: 32 KB L1 128 KB L2

⁵ Tera Operations Per Second

⁶ I/O PLL includes I/O bank I/O PLLs and fabric-feeding I/O PLLs.

⁷ You can repurpose the System PLL for core fabric usage if you do not use it for transceiver.