GTS CPRI PHY Intel® FPGA IP Design Example User Guide

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ID 814583
Date 1/13/2025
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. GTS CPRI PHY Intel® FPGA IP Design Example User Guide Archives 4. Document History for GTS CPRI PHY Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench
2. Design Example Description x
2.1. Features 2.2. Design Example Components 2.3. Simulation Design Example 2.4. Hardware Design Example 2.5. Interface Signals 2.6. Design Example Registers
2.2. Design Example Components x
2.2.1. Packet Client 2.2.2. Round Trip Counter 2.2.3. Sources and Probes 2.2.4. Avalon® Memory-Mapped Decoder 2.2.5. JTAG Host 2.2.6. IOPLL 2.2.7. System PLL 2.2.8. Reset Sequencer
1. Quick Start Guide
2. Design Example Description
3. GTS CPRI PHY Intel® FPGA IP Design Example User Guide Archives
4. Document History for GTS CPRI PHY Intel® FPGA IP Design Example User Guide

2. Design Example Description

The design example demonstrates the basic functionality of the GTS CPRI PHY Intel® FPGA IP. You can generate the design from the Example Design tab in the GTS CPRI PHY Intel® FPGA IP parameter editor.

To generate the design example, you must first set the parameter values for the IP variation you intend to generate.
Table 4.  Available Line Rates
CPRI Line Bit Rate (Gbps) RS-FEC Support Reference Clock (MHz)

Deterministic Latency Support
1.2288 No 153.6 or 122.88 Yes
2.4576 No 153.6 or 122.88 Yes
3.072 No 153.6 or 122.88 Yes
4.9152 No 153.6 or 122.88 Yes
6.144 No 153.6 or 122.88 Yes
9.8304 No 153.6 or 122.88 Yes
10.1376 Without 184.32 or 122.88 Yes
12.16512 Without 184.32 or 122.88 Yes
24.33024 Without 184.32 or 122.88 Yes
10.1376 With 184.32 or 122.88 Yes
12.16512 With 184.32 or 122.88 Yes
24.33024 With 184.32 or 122.88 Yes

Section Content
Features
Design Example Components
Simulation Design Example
Hardware Design Example
Interface Signals
Design Example Registers

Level Two Title