4.3.5. Limitations and Known Issues
Altera recommends that you read the information in the MIPI D-PHY IP User Guide, which describes the supported features in Agilex™ 3 and Agilex™ 5 FPGAs and the MIPI D-PHY IP. Each Agilex 5 device has specific limitations because of bonded pin availability.The B18A package provides a limited number of lanes for D-PHY interfaces, with available bonded pins between BYTE4 to BYTE7. Conflicts may arise between the RZQ pin and data lane pins. For placement rules, refer to MIPI D-PHY User Guide.
In this release, the MIPI CSI-2 IP provides support for between one and four virtual channels. The IP supports 4-bit virtual channel IDs (VCIDs) using CSI-2 virtual channel extension (VCX) signaling, but only processes VCIDs 0 to 3. The IP does not process VCIDs 4 to 15 and drops any video data using these extended VCIDs. Packet headers must contain 6-bit ECC and 4-bit VCIDs. The receiver supports between one and four virtual channels in all data types except YUV420 formats, where one virtual channel only is supported.
Video line length and RX AXI-S line blanking must be an integer multiple of the CSI-2 data type packing multiple. For example, multiples of four pixels for RAW10, where four 10-bit pixels are packed into five bytes. The MIPI CSI-2 specification defines the packet data size constraints for each data type.
The IP supports interlaced video only when you insert MIPI line start and line end packets into the stream according to the CSI-2 standard.
When operating with relatively low DPHY line rates, e.g. below 400 Mbps, the MIPI CSI-2 receiver may not produce a video output. The reason is the source provides insufficient clock pulses in the HS-TRAIL period following HS data transmission. A solution is to increase the TCLK-POST or THS-TRAIL values on your CSI-2 source.
When upgrading CSI-2 receiver IP originally generated in Quartus Prime v24.2, you may need to delete and recreate the the CSI-2 IP, because of a parameter problem in that version.