MIPI CSI-2 IP User Guide

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ID 813926
Date 3/30/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the MIPI CSI-2 IP 2. MIPI CSI-2 IP Interfaces 3. MIPI CSI-2 IP Parameters 4. Designing with the MIPI CSI-2 IP 5. MIPI CSI-2 IP Block Descriptions 6. Registers 7. Document Revision History for MIPI CSI-2 IP User Guide
1. About the MIPI CSI-2 IP x
1.1. MIPI CSI-2 IP Features 1.2. Device Family Support for MIPI CSI-2 IP 1.3. Recommended Speed Grades for MIPI CSI-2 IP 1.4. MIPI CSI-2 IP Performance and Resources 1.5. Release Information for MIPI CSI-2 IP
2. MIPI CSI-2 IP Interfaces x
2.1. MIPI CSI-2 IP Clocks 2.2. MIPI CSI-2 IP Resets 2.3. MIPI CSI-2 IP User Interfaces
2.3. MIPI CSI-2 IP User Interfaces x
2.3.1. Receiver PPI Signals 2.3.2. Avalon® Memory-Mapped Interface Control Interface Signals 2.3.3. Receiver AXI4-Stream Output Video Interface Signals 2.3.4. Receiver AXI4-Stream Output Passthrough Interface 2.3.5. Transmitter PPI Signals 2.3.6. Transmitter AXI4-Stream Input Video Interface Signals 2.3.7. Transmitter AXI4-Stream Input Passthrough Interface
4. Designing with the MIPI CSI-2 IP x
4.1. Generating the MIPI CSI-2 IP 4.2. MIPI CSI-2 IP Generation Output Quartus® Prime Pro Edition 4.3. MIPI CSI-2 IP Systems Integration and Implementation
4.2. MIPI CSI-2 IP Generation Output Quartus® Prime Pro Edition x
4.2.1. Files Generated for the MIPI CSI-2 IP and Platform Designer Systems
4.3. MIPI CSI-2 IP Systems Integration and Implementation x
4.3.1. D-PHY PPI Clock Frequencies 4.3.2. MIPI CSI-2 Receiver Clock Requirements 4.3.3. MIPI CSI-2 Transmitter Clock Requirements 4.3.4. Required Supporting IP 4.3.5. Limitations and Known Issues 4.3.6. Troubleshooting
5. MIPI CSI-2 IP Block Descriptions x
5.1. MIPI CSI-2 Receiver 5.2. MIPI CSI-2 Transmitter
6. Registers x
6.1. CSI-2 Receiver Register Map 6.2. CSI-2 Transmitter Register Map
1. About the MIPI CSI-2 IP
2. MIPI CSI-2 IP Interfaces
3. MIPI CSI-2 IP Parameters
4. Designing with the MIPI CSI-2 IP
5. MIPI CSI-2 IP Block Descriptions
6. Registers
7. Document Revision History for MIPI CSI-2 IP User Guide

1.4. MIPI CSI-2 IP Performance and Resources

Shows the typical device resources for selected configurations using the Quartus® Prime Pro Edition software. The number of ALMs and logic registers are rounded up to the nearest 50. The number stated for M20K memory blocks includes no rounding.

Changing pixels-in-parallel or data type has little impact on resources, though selecting multiple data types does increase logic.

The device type (Agilex 3, Agilex 5 E-Series, or Agilex 5 D-Series) makes no difference.

Table 3.  CSI-2 Receiver Performance and Resources

Turning off ECC and CRC checking, and removing the Control and status registers reduces logic to around 35% of these values.

Passthrough reduces logic to around 75%.

Configuration ALMs Logic Registers M20K Memory Blocks
Data Lanes Pixel-in-Parallel Number of Interfaces Data Type
1 2 1 RAW8 2,550 4,900 6
1 2 4 RAW8 3,800 7,050 18
2 2 1 RAW8 2,650 5,150 8
2 2 4 RAW8 3,950 7,400 20
4 2 1 RAW8 3,450 6,350 12
4 2 4 RAW8 4,650 8,650 24
8 2 1 RAW8 5,200 8,950 20
8 2 4 RAW8 6,450 11,300 32
Table 4.  CSI-2 Transmitter Performance and Resources

Turning off ECC and CRC insertion (which is against the specification and hence not recommended), and turning off the Control and status registers reduces logic to around 70% of these values.

Passthrough reduces logic to around 25%.

Configuration ALMs Logic Registers M20K Memory Blocks
Data Lanes Pixel-in-Parallel Number of Interfaces Data Type
1 2 1 RAW8 2,050 3,750 8
1 2 4 RAW8 3,800 6,450 11
2 2 1 RAW8 2,050 4,150 8
2 2 4 RAW8 3,750 7,250 11
4 2 1 RAW8 2,550 4,650 8
4 2 4 RAW8 4,350 7,250 11
8 2 1 RAW8 4,200 6,900 10
8 2 4 RAW8 6,000 9,300 13
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