MIPI CSI-2 IP User Guide

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ID 813926
Date 3/30/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the MIPI CSI-2 IP 2. MIPI CSI-2 IP Interfaces 3. MIPI CSI-2 IP Parameters 4. Designing with the MIPI CSI-2 IP 5. MIPI CSI-2 IP Block Descriptions 6. Registers 7. Document Revision History for MIPI CSI-2 IP User Guide
1. About the MIPI CSI-2 IP x
1.1. MIPI CSI-2 IP Features 1.2. Device Family Support for MIPI CSI-2 IP 1.3. Recommended Speed Grades for MIPI CSI-2 IP 1.4. MIPI CSI-2 IP Performance and Resources 1.5. Release Information for MIPI CSI-2 IP
2. MIPI CSI-2 IP Interfaces x
2.1. MIPI CSI-2 IP Clocks 2.2. MIPI CSI-2 IP Resets 2.3. MIPI CSI-2 IP User Interfaces
2.3. MIPI CSI-2 IP User Interfaces x
2.3.1. Receiver PPI Signals 2.3.2. Avalon® Memory-Mapped Interface Control Interface Signals 2.3.3. Receiver AXI4-Stream Output Video Interface Signals 2.3.4. Receiver AXI4-Stream Output Passthrough Interface 2.3.5. Transmitter PPI Signals 2.3.6. Transmitter AXI4-Stream Input Video Interface Signals 2.3.7. Transmitter AXI4-Stream Input Passthrough Interface
4. Designing with the MIPI CSI-2 IP x
4.1. Generating the MIPI CSI-2 IP 4.2. MIPI CSI-2 IP Generation Output Quartus® Prime Pro Edition 4.3. MIPI CSI-2 IP Systems Integration and Implementation
4.2. MIPI CSI-2 IP Generation Output Quartus® Prime Pro Edition x
4.2.1. Files Generated for the MIPI CSI-2 IP and Platform Designer Systems
4.3. MIPI CSI-2 IP Systems Integration and Implementation x
4.3.1. D-PHY PPI Clock Frequencies 4.3.2. MIPI CSI-2 Receiver Clock Requirements 4.3.3. MIPI CSI-2 Transmitter Clock Requirements 4.3.4. Required Supporting IP 4.3.5. Limitations and Known Issues 4.3.6. Troubleshooting
5. MIPI CSI-2 IP Block Descriptions x
5.1. MIPI CSI-2 Receiver 5.2. MIPI CSI-2 Transmitter
6. Registers x
6.1. CSI-2 Receiver Register Map 6.2. CSI-2 Transmitter Register Map
1. About the MIPI CSI-2 IP
2. MIPI CSI-2 IP Interfaces
3. MIPI CSI-2 IP Parameters
4. Designing with the MIPI CSI-2 IP
5. MIPI CSI-2 IP Block Descriptions
6. Registers
7. Document Revision History for MIPI CSI-2 IP User Guide

1.3. Recommended Speed Grades for MIPI CSI-2 IP

The following table shows the recommended speed grade when axi4s_clk runs at certain clock frequencies. To calculate the required clock frequency, refer to Transmitter Clock Requirements.
Table 2.   Recommended Speed Grades
Device axi4s_clk Frequency (MHz) Speed Grades
Agilex 5 D-Series <450 -3, -2, -1
450 to 500 -2, -1
Agilex 5 E-Series (Group A) <400 -3, -2, -1
400 to 500 -2, -1
Agilex 5 E-Series (Group B) <250 -6, -5, -4
250 to 300 -5, -4
300 to 400 -4
Agilex 3 <250 -7, -6
250 to 345 -6
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